By Debra Vogler, senior technical editor
April 13, 2011 — New work from Stanford University goes beyond simple bump shear testing to allow simulation of stresses exerted on chips during semiconductor packaging. The researchers are able to explore how the stresses affect back-end structures.
Alex Hsing, a PhD student in Professor Reinhold Dauskardt’s Group at Stanford University, will be presenting a paper titled "Shear microprobing of chip-package interaction in advanced interconnect structures" at the IITC 2011 Conference (May 9-12, Dresden, Germany). In a podcast interview, Hsing summarizes the key results of the paper and explains how the group’s approach differs from simple bump shear testing.
Listen to Hsing’s interview: Download or Play Now
The researchers used a microprobe metrology system to evaluate advanced interconnect structures, studying a bump-over-pad design vs. an RDL design at three temperatures (room temperature, 50ºC, and 100ºC). At room temperature and 50ºC, the bump over pad design and the RDL design behave in a "relatively comparable manner." However, at 100ºC, the bump over pad design weakens significantly compared to the RDL design (see the figure). They concluded that the "comparatively lower temperature sensitivity of critical failure stress of the RDL design suggests that it may offer an advantage at high temperature," as noted in the paper. The group showed that shear stresses cause damage that can quickly propagate through multiple levels of metal.
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Figure. Critical failure stresses for the bump over pad design and the RDL design plotted as a function of pad size at 100ºC in the stronger direction (a), and in the weaker direction (b). |
Hsing also addresses the anticipated "hot button" issues that will likely come up at the conference, and the next steps the researchers will take, (e.g., imaging methods will be needed to pair up with the metrology system described in the current paper).
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