by Michael A. Fury, Techcet Group

April 28, 2011 – Day 3 of the MRS Spring 2011 meeting kept me close to my roots, with most of the day spent in the symposium on materials, processes and reliability for advanced interconnects. NVRAM options were my primary distraction from this mission, giving me a reason to move around instead of sitting all day in one place.

I will never understand the point of giving a public presentation at an open forum such as MRS in which every slide is emblazoned with "Confidential Information." If all of your information is this confidential, then it isn’t. My baby engineer training at IBM was apparently well-ingrained, as this misuse of confidentiality labeling still makes me cringe.

(Additional presentation details can be found online on the MRS Spring 2011 abstracts page. The underscored codes at the beginning of papers reviewed below refer to the symposium, session, and paper number.)

InGaAs-on-Si, hardmask showdown, Cu via reliability, flexible electronics

Mitsuru Takenaka of the U. of Tokyo (P5.4) spoke on InGaAs MOS devices on Si. Metal source/drain is required due to limited dopant solubility; Ni has been found to be a good candidate because it forms a good alloy with InGaAs, and Ni can be selectively etched with HCl without affecting the underlying material. Device gate leakage was very low due to the successful removal of excess Ni. Source/drain resistance with Ni is 5× lower than with pn junctions. A fully integrated p Ge and n InGaAs circuit will be presented later this year at the VLSI conference in Kyoto. Examples of III-V photonic devices on Si were also shown.

Olivier Joubert from CNRS in Grenoble, France (O4.1) compared damascene process strategies with metal hard mask to an amorphous carbon hard mask. With the carbon mask, CD control can be an issue due to faceting of the Si-ARC layer during carbon etch. In subsequent etching of the p-SiCOH, control of bowing can be difficult. It is preferred that the low-k material remain hydrophobic to limit uptake of moisture which increases the k value; strategies to ensure this are not well understood. With metal mask, maintaining sidewall profile becomes difficult if the TiN mask is exposed during p-SiCOH etch, due to Ti byproducts interfering. Raising the process temperature from 20°C to 60°C reduces this effect, as the Ti byproducts are more volatile and less likely to interfere. Post-etch treatment with CH₄ eliminates the TiF residues that can form during the queue time between plasma etch and hard mask stripping.

Kazuaki Yazawa of UC Santa Cruz (O5.4) used a thermoreflectance microscopy imaging technique to explore copper via chain reliability. Changes in temperature profile over time suggest the ability to determine characteristics of voiding mechanisms and specific locations, but these remain to be further developed.

Ben Schlatka of the U. of Illinois @ Urbana (HH4.4) used an mc10 presentation to illustrate a variety of applications for flexible and stretchable electronics, particularly those coming out of John Rogers’ lab. Semprius, another Rogers spin-out, provides the assembly technology to pick and place the extremely thin Si devices from the host wafer to the target flexible substrate. Stretchable PV is achieved using small individual GaAs cells and buckled interconnects, providing up to 20% stretch. Applications include solar power for a tent, or an unmanned air vehicle in which the wing surface can generate electric power. In partnership with Reebok, an announcement will be made later this year for personal fitness and performance monitoring. Skin-mounted devices are coming for both health care and for human-computer interfacing. The long-term product development for in vivo medical care, which is FDA regulated and requires expensive certification, will be funded by short-term development cycle consumer products.

Memory

Roberto Bez of Micron/Numonyx (Q3.1) provided a status report on advances in NVRAM, primarily phase-change memory (PCM). Ten-year retention is a long time for an old device to sit in the back of the closet, but that’s the design objective. Among the most interesting options are flash, STT-MRAM, RRAM, and PCM. The 45nm 1Gb PCM chip is in volume qualification, using Ge₂Sb₂Te₅. Diffusion effects under operating conditions mean that the local stoichiometry is not uniform, nor is it equivalent to the composition deposited. One possible result is void formation and loss of reliability.

Hongsik Jeong of Samsung (Q3.6) gave his perspective on the status of PCM (which Samsung calls PRAM) as the next NOR technology. They are currently producing a 1Gb 45nm device. The technology is thought to be scalable to 10nm, with the advantage that the operating power scales down with the contact area.

Jong Moon Yoon at KAIST (Q3.8) showed a multilevel PCM scheme using a trilayer PRAM cell array in which each PCM volume has two separate TiN electrodes and two separate crystallization regions, thereby providing three distinct resistance levels per cell. The group was able to fabricate a device with a memory density of 207 Gbit/in².

Benjamin Kam at IMEC (Q5.1) described an organic ferroelectric FET memory device based on a low-leakage P(VDF-TRFE) layer. The programming voltage can be limited to ±15V by using a P(VDF-TRFE) thickness of 200nm. Leakage currents of 10^-9 A/mm² at 1 MV/cm are exceptionally low.

Philipp Sebastian at TU Dresden (Q5.6) described an organic ReRAM device based on C₆₀ buckyballs. The device is read at +1V, written at +4V and erased at -4V, with an on/off ratio of 10. R/W time is 50μsec, durability is 10⁴ cycles, and the retention time of weeks is dependent on the interim readout frequency.

Mikhail Dronov of the General Physics Institute in Moscow (Q5.7) showed a new memory device concept based on an organic MEH-PPV layer mixed with 5μm particles of Zn or Fe-Ni alloy. R_ON/R_OFF is 10⁶, with switching times of 100ns to turn on, 1μs to turn off. Durability was tested to 10⁴ cycles with no degradation. Retention >3 months is believed to be due to filament formation. Addition of a photoactive compound to the organic layer allows the device to be turned on by light, with retention comparable to electrical switching, but this cannot be explained by filament formation.

Low-k dielectrics

Sven Zimmermann of Fraunhofer ENAS (O4.2) proposed a process flow to reduce damage in ultralow-k (ULK) integration. Modifications of the etch chemistry can reduce the k damage by promoting CH₂ species and maintaining hydrophobicity. HMDS was chosen as a k repair medium by immersion at 150°C followed by 2min UV exposure, which reacts with the near-surface damage but not the bulk.

Theo Frot from IBM (O4.3) proposed a ULK-friendly integration scheme called post-porosity plasma protection, or P4. The k=2.0 material is based on Et-OCS. After dielectric formation, pores are filled with a separate polymer material to protect the porosity structure during etch. The secondary polymer is removed following etch at 400°C in N₂. Electrical results will be reported at IITC next month (May 2011).

Griselda Bonilla of IBM Watson (O5.1) addressed several of the key reliability issues associated with low-k dielectric materials. The primary parameters monitored are EM, TDDB and CPI reliability. Defects do not scale, and the majority of TDDB failure mechanisms become worse with ULK materials. J_USE drops 2× with each generation and may constitute a fundamental electromigration scaling limit as the copper mass continues to decrease. ULK energy release rate can be 30% higher than low-k, providing another driving force for mechanical reliability problems.

Barrier materials

Expressing his relief to be back in a region that allows for a normal life — though some of our more conservative citizens might question whether San Francisco actually qualifies — Junichi Koike of Tohoku U. in Sendai, Japan (O6.1) spoke on the attributes of CVD MnO as a copper barrier layer. The barrier forms as an embedded layer in the dielectric, but the barrier-dielectric interface can form an undesirable high-k dielectric; for example, MnO-TEOS can be as high as k=10.7. The CVD MnO was deposited from Mn(EtCp)₂ to a thickness of 3-4nm with good step coverage even at the via bottom. MnO adhesion was good at a deposition temperature up to 300°C; above 400°C the precursor pyrolizes, increasing carbon content and decreasing adhesion. Dielectric breakdown was 4MV/cm at 550°C, indicating good barrier function.

Shaoning Yao from IBM (O6.2) continued the Mn barrier theme with a CuMn alloy seed layer to improve electromigration results. This is used in conjunction with the conventional Ta/TaN barrier, not as a replacement for it, and was successfully integrated at 32nm. Line depletion failure improves by 10×-25×. Further a non-gouging liner (TaN/Ta/CuMn at the via bottom) performed 2× better than a gouging liner (no TaN at the via bottom).

Neda Dalili of the U. of Alberta (O6.3) took a look at amorphous TaN as a copper diffusion barrier. During anneal at 500°C-800°C, TaSi forms in samples of TaN on Si when there is copper present on top of TaN, but not when there is no Cu present. With Cu, the barrier integrity is preserved to 700°C, but at 800°C the TaN barrier fails and Cu₃Si forms. Amorphous TaN crystallizes to Ta₂N above 500°C, and the volume displacement defects allow Cu diffusion to occur.

Ryan Birringer at Stanford (O5.2) studied the adhesion of barrier materials to copper and related properties. Impurities in the barrier films tend to promote stress-induced void formation, which in turn leads to surface fracture and adhesion degradation. HKMG systems were also studied.

Deposition

Taehoon Cheon at Yeungnam U. (Korea) (O6.7) has an ALD process for RuAlO barrier films that enable direct Cu plating without a seed layer. Ru is not suitable by itself as a Cu barrier due to its polycrystalline columnar grain structure. This ternary Ru alloy is one of several that have been proposed. Films are formed at 225°C using Ru(EtCp)₂ and Al(CH₃)₃ ALD deposition super cycles up to a ratio of 40:5. Excellent conformality was demonstrated in an AR=32 trench. Direct plating of Cu without a seed was shown with good adhesion.

Sanghyuk Choi at Yeungnam U. (O6.8) spoke about the deposition and plating properties of ALD Ru barrier using the zero valence Ru precursor described in Cheon’s talk. Growth rate was 0.08nm/cycle with negligible incubation cycles of ~9, indicating the rapid nucleation of Ru. The deposition is self-limiting, indicating a surface reaction and not thermal decomposition. Adhesion on Ta was comparable to PVD Ru. Resistivity was 15μΩcm with a polycrystalline columnar grain structure.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].