MRS Day 4: Outside CMOS fabrication, but respecting boundaries

by Michael A. Fury, Techcet GroupClick to Enlarge

April 28, 2011 – Day 4 of the MRS Spring 2011 meeting afforded me a bit more opportunity than yesterday to spend time outside of core CMOS issues. Screen printing with 80ft2 screens, for example, is pretty far afield from submicron fabrication methods. 3D integration was one focus for today, and there are a number of applications outside of electronics that are driving new printing and additive fabrication methods that may well serve the needs of the electronics industry.

Observation of the day: Session chairs come with a broad range of sensitivity to time and schedule. Flexibility and collegial discussions are welcome in single symposia, as they make good use of the extended knowledge and experience of people who have gathered from all over the world. But when the symposium is part of a 51-arm synchronized hydra, strict adherence to the printed schedule is a professional courtesy that needs to be uniformly respected.

MRS Spring 2011
Day 1: Lighting the paths for LED materials
Day 2: The III-V future of CMOS, the return of spin-on low-k
MRS Day 3: Memory, hardmasks, low-k — nothing’s confidential
Thin-film PV materials under the microscope @ MRS

(Additional presentation details can be found online on the MRS Spring 2011 abstracts page. The underscored codes at the beginning of papers reviewed below refer to the symposium, session, and paper number.)

Microdevices

Tsu-Jae King Liu of UC Berkeley (Q8.1) spoke about the use of NEMS devices for nonvolatile memory (NVRAM) applications, called NEMory. ION/IOFF and endurance for such devices are effectively ∞, with no radiation or shock sensitivity. By using an ONO charge trap nitride in the structure, the cantilever bias voltage can be adjusted to 0V, creating a bistable NV storage system with no power applied. Devices shown used an Al or TiN cantilever 0.1μm thick. Either the cantilever or the electrode must be coated with a thin oxide to avoid metal contact welding. In principle, the material set and fabrication methods are CMOS compatible and could be integrated into the on-chip interconnect levels. The ONO film only needs to be charged once, so a thick layer can be used, providing a 10-year retention time. Power consumption is two to six orders-of-magnitude lower than competing NVRAM technologies.

Virginia Chu from INESC Microsistemas e Nanotecnologias, Lisbon, Portugal (A13.1) talked about several applications of amorphous Si for the fabrication of MEMS and NEMS devices. Flex-mode resonators move out of plane and can suffer loss of Q in dissipative media, whereas bulk-mode resonators move in plane and can maintain a high Q in a variety of media. Bulk devices can also operate at a higher sustained resonance frequency. One device of interest is a magneto-resistive spin valve magnetic field detector that can sense deflections to 0.03Å optically and 0.06Å magnetically. Using flux concentrators, the device is being refined to sense the magnetic fields generated by human brain activity on the order of 10-12 Tesla (earth’s magnetic field is 10-4T).

Organic electronics

Stephen Forrest at the U. Michigan (T6.1) described the patterning of μm-scale organic electronics using organic vapor jet deposition. This is analogous to CVD TEOS vapor transport using a bubbler, except that in this method the organic source is deposited in its original form without decomposition. Patterning by shadow mask produces material gradients and poor edge definition that limit feature sizes to ~5μm. Nozzles are fabricated in Si with a resolution limit of printing 1.5μm features and a 30cm/sec substrate feed. It would take 25sec to print a 60" OLED display, but note that the method is more comparable to spray painting than to inkjet printing, as there is no on-off mechanism as presently implemented. Angstrom Engineering is their equipment development collaborator.

Tsuyoshi Sekitani from the U. of Tokyo (T6.2) showed some examples of large area (no, really large — 3.3m×3.5m screens!) screen printing of organic ICs with an accuracy of 20μm. On a smaller scale in their lab, they developed a new twill weave mesh material with high tensile strength (3000 N/mm) capable of tolerating very high viscosity silver inks that could deliver 25μΩcm resistivity with ambient temperature drying. This enabled formation of organic thin-film transistors with a 1mm cell pitch, not good enough for displays but adequate for sensors and other devices. Mobility was on the order of 0.1cm2/Vs. A PMOS unipolar inverter had a gain of 2, a CMOS circuit had a gain of 80. This screen print method was used to fabricate a flexible touch sensor sheet and a plastic mechanical switch array.

Extending the organic electronics themes from Forrest’s talk, Max Shtein at the U. of Michigan (T6.3) discussed the vapor jet printing of OLED and OPV materials. Among the objectives is the deposition of volatile organic materials without the use of solvents. Material flow is focused using a concentric guard flow of nitrogen or other low molecular weight gas. As guard flow rate increases, performance of Alq3, which is air and moisture sensitive, approaches that of vacuum-deposited material. Parylene CVD can be accomplished with the system by passing the precursor through a high temperature zone, which cracks the dimer to a monomer, then depositing the monomer on the substrate where it polymerizes.

Deposition

Francisco Zaera at UC Riverside (O7.5) studied the use of copper amidinate bis[(N,N’-di-sec-butylacetamidinate)Cu] as an ALD precursor. ALD monolayer behavior is observed at a deposition temperature of 350°K but at 400°K it is already behaving like CVD. A full monolayer of copper on a nickel substrate was achieved in 3-4 deposit/anneal cycles.

Avraham Rozenblat from Micron and Tel Aviv U. (O7.6) reviewed nucleation issues in the application of CVD tungsten below 45nm. Via shrinks decrease the bulk material and increase the interface contribution to via resistance. Over the deposition range of 290° C to 340° C on a Ti/TiN substrate, the resistance drop saturates at an average film thickness of 26nm regardless of temperature. Nucleation gives way to surface percolation conductivity before saturating with complete surface coverage.

Jon Gudmundsson at the U. of Iceland (O7.7) talked about the growth of ultra-thin TiN films on SiO2 using high-power impulse magnetron sputtering (HiPIMS), which produces crystallites smaller than DC magnetron sputtering but with a 30% lower deposition rate. On a MgO substrate compared to SiO2 substrate, the coalescence thickness drops from 1.09nm to 0.08nm, and the continuous film thickness drops from 5.5nm to 0.7nm. Films grown at 500°C are resistant to oxidation, indicating high density, and have a low resistivity of 54μΩcm on SiO2 and 16.6μΩcm on MgO.

Yair Ein-Eli at Technion-Israel Institute of Technology (O7.8) described a method for seedless electrodeposition of copper on Ta using an alkaline plating bath. It is expected to be applicable to Ru, Ru/Ta and other barrier metals that form a native oxide. Electrochemical studies were carried out in a K4P2O7 medium (pH 9.3). Native Ta2O5 oxide was first electrochemically reduced to metal, then copper solution with 3ppm DMcT were added and the potential was moved from -2V to -1.2V for deposition.

Cu TSVs, packaging tests, 3D interconnects

Arif Budiman from LANL (O8.3) studied mechanical stresses in copper through-silicon vias (TSV) using in situ synchrotron X-ray submicron diffraction. Grain size and stress mapping of the Cu within the via and of the Si itself during the post-deposition anneal proved itself to be a useful tool for understanding the mechanism behind via popping. All you need is a synchrotron.

Hae-A-Seul Shin of Seoul National U. (O8.4) talked about the evolution of damage during thermal cycling of Cu TSV studied with FIB, EBSD, and synchrotron XRD (yes, she used the same synchrotron in Berkeley as in the study above). Grain structure was found to be stable for 1 year following a 200°C anneal, thought to be due to the abundant presence of twin grain boundaries. Annealing reduced the average hydrostatic stress in the Cu from 229MPa to 177MPa due to the formation of voids and cracks.

Alexander Hsing at Stanford (O8.2) demonstrated the use of a suite of microprobe test methods for compressive, tensile and shear loading capabilities of Pb-free solders and structures used in chip bumps, pads and other electronic packaging schemes. The metrology operates at nanoscale dimensions lower than that used in conventional techniques.

Xiaopeng Xu from Synopsys (O8.5) described a simulation test method for evaluating stresses in microbump and underfill systems for a range of bump diameters, underfill materials, and geometry layouts. The effects of process sequence and annealing profiles were examined. It was observed that the chip regions with the largest device performance variation are not necessarily the same as the regions where the structure reliability is a greatest risk.

Owen Hildreth at Georgia Tech (O8.6) introduced metal assisted chemical etching (MaCE) for use in 3D interconnects. The metal catalyst moves into the Si substrate with the etch front, preserving the profile with etch depth. A shaped catalyst can create features not possible with other methods; for instance, an asymmetric catalyst will rotate as the etching proceeds, producing a hole with sidewall threads, like a screw. Such a via hole would provide mechanical adhesion for a TSV rather than relying only on interfacial adhesion.

Nanostructures and nanoparticles

Marco Rolandi of the U. of Washington (T7.6) talked about direct write of Si, Ge, and SiGe nanostructures using a biased AFM tip, a form of dip-pen nanolithography, an interesting technique with limited application in the manufacturing world. Productivity was increased by using a patterned gold-coated PDMS stamp. The ink was diphenyl silane or germane. Characterization of the deposited material showed high quality, carbon-free material by SIMS and X-ray PEEM. A roadmap for further improvement of the technique was shown.

Eric Duoss of the U. of Illinois @ Urbana (T7.7) taught us about direct-write assembly of functional inks for conductive microstructures. Today’s lesson covered a silver nanoparticle ink fabricated with a 20nm average particle size with a range of 5nm-50nm. Control of the ink velocity permits conformal printing or true 3D printing. Using up to a dozen passes, 3D features with an aspect ratio of 7 can be fabricated. Stacked chip joining was demonstrated by printing across an air bridge between the chip and the substrate below. This is possible because the ink dries so quickly as it exist the nozzle, making it, in effect, a fluid bonding wire that is available on demand. Conformal printing on hemispherical surfaces can be used to fabricate low Q antennas for mobile communications devices.

Printed electronics

Romain Cauchois from Gemalto (France) (O8.9) tailored the crystallographic texture and electrical properties of inkjet printed interconnects to optimize performance for RF and related applications. Their system operates with 30pL drops of a commercial silver ink with 30-40nm particles. Sintering is accomplished at 200°C using a rapid ramp of 150° C/min. Silver grain growth was also augmented by depositing a thin gold layer before the silver features, which resulted in a fiber texture that was not otherwise achievable. The resulting structure proved to improve wire bonding results over the conventional process.

PV

Bill Nemeth of NREL (A16.5) talked about use of a light down shifting (LDS) thin-film coating to improve the performance of a-Si:H solar cells. The concept is to use the wasted light that is not otherwise absorbed by the cell by shifting the frequency of the light that falls outside of the cell’s peak absorption range. Down shifting differs from down conversion in that shifting implies a conversion efficiency <100%. Instead of the expected current gain of 0.28mA/cm2, they saw a loss of 0.13mA/cm2. This was attributed to side scattering due to nonoptimized experimental conditions. They will try again.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected]

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