April 20, 2011 — Current work developing silicon interposers takes advantage of existing and depreciated 200 and 300mm wafer fabs, using back end of line (BEOL) tools and processes as well as the newly developed TSV technology for 3D ICs. Georgia Tech PRC believes such silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers.

Silicon interposers made this way will be too expensive for many consumer and smart phone electronics:

• Wafer-based approach results in small number of interposers; some of which may be as large as 30-50mm, thus driving up the cost of each;
• BEOL tools and processes are expensive for packaging applications;
• The TSV process is expensive for packaging as it uses DRIE and long-cycle time copper plating;
• The TSV requires an insulating liner such as SiO₂ that adds extra cost.

Georgia Tech PRC has undertaken silicon R&D with the potential to reduce the cost by 5-10x, by addressing the above issues. Specifically, the research:

• Uses a panel-based approach that can be scaled to 10X higher in throughput;
• Uses polycrystalline silicon, a lower cost Si material;
• Uses 200µm-thick silicon without chemical-mechanical polish;
• Is developing a lower cost through via process without DRIE and SiO₂ liner;
• And is developing low cost, double-side process for RDLs.

This technology is under development at Georgia Tech PRC with a large research team, in partnership with more than 15 global companies from the US, Japan, and Europe, as part of its Silicon and Glass Interposer Industry (SiGI) Consortium. Georgia Tech hopes to develop this exciting technology to demonstrate highest I/O density at lowest cost in smallest size to become the new de-facto standard interposer technology for future electronics.

Companies interested in joining this silicon interposer research program are encouraged to contact Dr. Venky Sundaram at [email protected] or Prof. Rao Tummala at [email protected]. Learn more at www.prc.gatech.edu

Also read: IMAPS: 3D IC toolset readiness, Cu bonding, interposer failings

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