Surface preparation for 2011 and beyond

Executive Overview

While front-end-of-line (FEOL) processes still drive cleans related development, the challenges encountered by surface preparation engineers extend well beyond this traditional area of concern. Today’s technology demands attention throughout the entire process flow and significant challenges must still be identified and solutions developed. Surface preparation engineers are tasked with discovering and implementing novel cleaning techniques and chemicals in all areas of manufacturing.

Joel Barnett, SEMATECH, Austin, TX, USA

Although the requirements outlined in the surface preparation table in the Front End Process section of the International Technology Roadmap for Semiconductors (ITRS) have changed only incrementally over the past few years, FEOL cleans have historically driven wafer cleaning requirements. However, while the number of cleaning processes in a process flow have increased, the relative number of FEOL cleans has declined significantly, to about 1/3 of the total cleans (Fig. 1). Front-end cleaning processes will continue to be impacted by the introduction of new front-end materials such as high-k dielectrics, metal gate electrodes, and mobility-enhanced channel materials.

Figure 1. Number of cleans per logic node. SOURCE: Cameo Consulting/used with permission.

In the ITRS, the Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield. The "killer defect" size (i.e., the critical particle diameter) continues to decrease based on the generation, scaling with DRAM half-pitch down to 20nm in 2011 (Fig. 2). Methods to remove contaminants of this size continue to rely on wet chemical methods, aided by megasonic or advanced non-damaging acoustic cleans, but they may also include aerosol (cryogenic, fluid) or nozzle-based particle removal, pulsed pressure, or vacuum techniques.

Figure 2. DRAM half-pitch critical particle size. SOURCE: SEMATECH

Scaling and cleans technology

Scaled devices are becoming increasingly shallow and/or fragile, requiring these cleaning processes to be benign in terms of substrate material removal, physical aggressiveness, and surface roughening. Achieving good particle removal efficiency and minimizing silicon loss without damaging fragile structures is also a significant challenge. The ITRS requirements of less than 0.2Å of film removal represent an average of multiple ash/clean steps on non-damaged polysilicon and oxide blanket test wafers. The numbers also represent the total silicon and oxide loss that can be tolerated for the combination of all post-gate, post-implant mask cleaning steps in which the extension areas are exposed. Too much material loss will deplete the dopant and subsequently degrade device performance.

While the introduction of thicker, high-k dielectrics and metal gate electrodes has allowed values for allowable on-wafer metal levels at pre-gate clean to remain constant, the challenges encountered in the gate module have increased. New materials and technologies require new photoresist techniques and challenges for photoresist and residue removal. These include multilevel resists, fluorocarbon-based residues with low material loss, no structural damage, and no impact to threshold voltage (Vt) or work function, while potentially being metal gate/high-k compatible. Some of the techniques being used today include new plasma chemical formulations, source technology, and advanced non-oxidizing processing. Success has also been achieved using a combined dry and wet cleaning approach, pre-treatment techniques for enhancing removal efficiency, and advanced wet cleaning.


Post-chemical mechanical polishing (CMP) cleaning has become a more critical application in FEOL and back-end-of-line (BEOL) as design for manufacturing (DFM) technologies and the integration of more CMP processes, especially as part of front-end device integration, challenge cleaning processes to deliver wafer surfaces with very low defectivity. These defects can adversely affect the electrical and reliability performance of semiconductor devices. After metal CMP processes, several defects can be generated on the surface, including particle deposition, organic deposition, voids, rip out, and scratches. The clean process must remove these defects without significant material loss, surface roughness, and/or corrosion issues. The practice of post-CMP brush scrubbing may not be appropriate at some levels.

To characterize killer defect density and enable yield learning, the surface preparation engineer must be able to reliably detect particles smaller than 20nm on a wafer surface. Confirmation of cleaning efficacy below 20nm is limited by the ability of current metrology to actually measure particles of this size, as well as the commercial availability of membrane filters to quantitatively sequester particles in this critical size range.

Defects and process problems around the wafer edge, bevel, and backside have been identified to cause yield problems. These contaminants must be removed without impacting the active portion of the wafer. It is understood that the lowest level of defects is desirable, but little data and few models are available that can link the size or density to yield on the front surface of the wafer. New SEMI guidelines are being developed to specify wafer edge roughness and other key parameters that impact die yield at the wafer edge.

As the industry moves towards materials requiring low temperature processing, controlling the interface before film deposition will become more critical. Sputtering and high temperature bake processes are no longer adequate for removing adsorbed molecular contamination such as carbon and oxygen, and it will be necessary to reduce surface carbon below the current spec of 1013 atoms/cm2. There is universal understanding that watermarks and drying-related defects cannot be tolerated on a cleaned surface. Controlled environments (e.g., FOUPS, clustered cleans) aqueous and subcritical solvent cleans, advanced passivants and formulations, and ultra-dry surfaces are all potential methods of controlling the interface.

Other considerations

The cleaning of extreme ultraviolet (EUV) masks is another difficult challenge. The availability of defect-free masks is one of the key requirements for the implementation of EUV lithography at the 22nm and 16nm half-pitch nodes.  The lack of a pellicle makes EUV masks prone to particle contamination. In addition, EUV masks introduce new materials and multilayer structures that are different from traditional optical masks. Physical forces used for particle removal on an optical mask might damage EUV mask patterns. Mask cleaning processes must remove all particles larger than 25nm without any damage to patterns.

BEOL cleans continue to be challenged by the need to seal low-k pores and to smooth roughness caused by plasma treatments. Additionally, as feature sizes shrink and aspect ratios increase, the difficulty of photoresist residue removal and proper contact clean increases. Because of their higher surface tensions and capillarity, water and solvents cannot easily penetrate into smaller vias and trenches.

Finally, surface preparation engineers must consider the impact on resources and the environment. Less chemical and water usage, chemical and water recycling, and alternative processes using less harmful chemistries, such as organic solvent-free formulations, can offer environment, safety, and health and cost-of-ownership benefits.


Advances in technology increase the challenges faced by surface clean engineers. They must discover new methods to realize contamination and surface termination requirements at each step of the manufacturing process, while simultaneously considering the impact to health, cost and the environment.


Joel Barnett received his BS in chemical engineering from the U. of California, Berkeley, and is a Senior Member of Technical Staff at SEMATECH, 2706 Montopolis Drive Austin, Texas 78741; ph.: 512-356-3500; email [email protected].

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