Gerald Beyer, Zsolt Tokei, imec, Leuven, Belgium

The main lithography workhorse for the creation of narrow patterns is immersion lithography utilizing a wavelength of 193nm. In a single exposure, patterns with an hp down to about 38nm can be printed. This performance does not, however, meet the resolution requirements for high density flash memory technologies and, in the near future, for logic technologies. Therefore, patterning approaches have been investigated to double the density of interconnect structures. The integration of single damascene structures with an hp of 20nm was recently reported using a spacer defined patterning approach [1]. An array of resist lines was printed with hp=40nm, which is close to the resolution limit of the scanner (Fig. 1). The width of the resist lines was reduced to 20nm by dry etch. The narrow resist lines served as a template for 20nm wide dielectric spacers that were created next to them. These spacers were then used to produce single damascene trenches in oxide. This approach is scalable to 15nm hp [2]. It requires, however, EUV lithography to achieve a higher resolution. To separate the lines electrically, it is necessary to remove parts of the spacer patterns in a second patterning step. The final interconnect pattern consists of metal lines running in a regular, parallel manner. This patterning approach has been adopted by the flash technology. It is expected that logic technology will consider spacer defined patterning as well for future technology nodes as a regular, gridded layout is becoming prevalent in logic [3].

Figure 1. Top and cross-section view of spacer defined patterning. With Mask 1 (top row) the spacers are created using 40nm hp resist lines. With mask 2 (first 2 drawing in middle row) the spacers loops are cut. With mask 3 (not shown here) the periphery such as electrical connections, etc., are defined before the trenches are etched into the dielectric and metalized at 20nm hp design rule (last 2 drawings in middle row). An example of a single damascene structure (cross-section TEM photo) is shown at the bottom row displaying Cu wires at 20nm hp.

Low-k dielectrics

When logic technology is to produce 20nm hp damascene structures the integration of low-k dielectrics will be challenged by the need to produce narrow dielectric spacings with high porosity. In the damascene approach trenches are etched into the dielectric. As the predominant low-k materials are based on a mixture of Si-O and Si-CH3 bonds, the preservation of the bond structure during the patterning process is of great importance for the mechanical stability and the capacitance of the dielectric spacing. As the Si-CH3 bond is thermodynamically weaker than the Si-O bond, a depletion of carbon is observed after patterning. This results in decreased hydrophobicity and k-value increase. At 20nm hp and high porosity, the width of the dielectric spacing is much smaller than the diffusion length of the plasma species in the SiOCH based dielectrics making the complete spacing prone to plasma damage. Additional treatments have been proposed to repair the damage to the Si-based porous low-k [4].

Figure 2. Median lifetime of organic polymer (k=2.2) exceeds the 10 year criterion for time-dependent dielectric breakdown measurements. The width of the dielectric spacing was systematically varied between 80 and 20nm (see TEM cross-section photos on the right).

Alternative materials with lower porosity or homogeneous bond structure are of strong interest to minimize the modification in the first place. Low-k dielectrics based on polymers incorporate both advantages. The C-H and the C-C bonds of the polymers have a lower polarization than the bonds of the Si based low-k dielectrics. Consequently, the porosity of the polymer can be reduced compared to the Si based dielectrics while keeping the k-value the same. The potential of a polymer dielectric was recently evaluated by modulating the width of the dielectric spacing from 80nm down to 20nm [5]. Even at the lowest width, the spacings were mechanically sound, but required more profile optimization to be electrically yielding. At 30nm width, the reliability of the dielectric spacings was on par with wider spacings. The median value of the time dependent dielectric breakdown lifetime exceeded the 10 years’ lifetime criterion (Fig. 2). Chemical analysis of the spacing did not reveal carbon depletion, which resulted in an integrated k-value of about 2.3, which is close to the as-deposited one of 2.2. These results indicate the potential of the polymer investigated to be incorporated at 20nm spacing without performance and reliability loss.

Metallization

Not only low-k integration, but also metallization, is at a cross roads at 20nm hp. The incumbent Ta-based barrier and copper seed layer could sustain the scaling of the wires down to about 30nm hp due to ever more ingenious physical vapor deposition technologies, which balanced the need for sufficient sidewall coverage and the reduction of overhang at the opening of the damascene structures. Below 30nm, it appears to be very challenging to tip this balance in favor of sufficient sidewall coverage. Consequently, voiding in the narrow Cu interconnect is frequently observed. Noble metal liners have been proposed and integrated with the purpose to enable plating on places of the sidewall where the Cu seed layer is patchy. Ru-based liners enable gap filling of sub-30nm structures [6].

At around 20nm hp, this three-layer system of barrier-plateable liner-Cu seed needs to be simplified as there is not enough space to accommodate all these layers in a narrow damascene structure and to do gap fill. One way of simplification is to remove the Cu seed layer and to plate directly on the liner. The liner is, however, more resistive than a Cu seed layer and requires a different approach to plating. Instead of plating the Cu uniformly over the wafer, the Cu deposition progresses from the edge of the wafer to the center. To achieve defect free filling by direct plating, a high nucleation density of Cu on the liner is required, which depends on the quality of the liner surface. There have also been attempts to incorporate barrier properties into the plateable liner by alloying the Ru layer with typical barrier metals such as Ta, Ti, Mn, etc. It remains to be seen whether these materials can accomplish the various functions at a thickness of 2nm and below.

Biographies

Gerald Beyer received his PhD from Imperial College, London and is the manager of the Nano Interconnect Program and the BEOL integration group at imec, Kapeldreef 75, 3001 Leuven, Belgium; ph.: +32-16-281894; email [email protected]

Zsolt Tokei received his PhD in materials science from the U. Aix Marseille-III, France and is the director of the Nano Interconnect Program at imec.

References

1. Y.K. Siew, et al., "Integration of 20nm Half-pitch Single Damascene Copper Trenches by Spacer-defined Double-patterning (SDDP) on Metal Hard Mask (MHM)," IITC2010.

2. J. Versluijs, et al., "Spacer-defined Double-patterning for Sub-20nm Half-pitch Single Damascene Structures," SPIE 2011.

3. K. Kuhn, "CMOS Transistor Scaling Past 32nm and Implications on Variation," ASMC2010.

4. S. Chikaki, "Ultralow-k/Cu Damascene Multilevel Interconnects Using High Porosity and High Modulus Self-Assembled Porous Silica," Jour. ECS, 157 (7), H519, 2010.

5. M. Pantouvaki, et al., "Advanced Organic Polymers for the Aggressive Scaling of Low-k Materials," SSDM2010.

6. L. Carbonel, et al., "Metallization of sub-30nm Interconnects: Comparison of Different Liner/Seed Combinations," IITC2009.

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