As several leading chip makers assert a more specific time line for 450mm pilot line development, pre-competitive collaboration will continue to be the best path towards economic efficiency and industry rationality. While uncertainly about development funding remains, the supply chain is marshalling SEMI Standards task forces to advance agreements on the technical parameters for 450mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has published six 450mm standards and 11 more are in the pipeline.
Jonathan Davis, SEMI, San Jose, CA USA
The relentless cost reduction and performance improvement of semiconductors is one of the most significant economic and social forces of the last half century. It transitioned the semiconductor industry into one of the world’s largest growth industries, helping improve and transform the lives of nearly everyone on the planet. A key driver behind this consistent ability to lower costs, improve performance and create new markets has been industry collaboration — the ability of the world’s smartest people to collectively work together to expand the industry. Pre-competitive collaboration systems like the International Technology Roadmap for Semiconductors (ITRS), SEMI International Standards, and other systems empowered Moore’s Law for a generation, focusing scarce R&D resources.
As the marketplace has consolidated and become truly global, industry organization and collaboration continues to be the foundation for progress and profitability. Not long ago, we faced the deepest industry slump in our 50-year industry; many fine companies did not survive the collapse in chip demand. Today, the economic outlook is brighter, but our industry remains vulnerable. As the global supply chain — IDMs, foundries, fabless chip companies and suppliers — approaches the multi-dimensional choices related to wafer size transition, pre-competitive collaboration continues to be the best path.
A credible or broadly-accepted 450mm wafer size transition scenario that validates overall economic benefit for the industry has yet to materialize. Many equipment companies and their suppliers remain skeptical about the business implications of a wafer size transition and uncertain about the funding for necessary development. However, several leading chip makers recently have been more assertive and specific about pilot line timing. A likely scenario — that involves participation of chip makers, policy makers, academic and research organizations, equipment and materials companies — is pressing forward, though many details remain closely guarded at the time of this writing.
Nonetheless, one thing is certain. If the transition is to ramp in the time frame desired by the primary proponents, much needs to be done to align industry activity, create efficiencies and agree on the fundamental specifications that enable development progress. To this end, the international standards community, working within the time-tested format of the SEMI International Standards program, has paved the way for necessary pre-competitive collaboration that is so essential for a successful transition.
ISMI has been active in supporting 450mm wafer development and material handling requirements through a number of programs and demonstration projects. They have created a "wafer bank" to lend test wafers to equipment developers, developed an interoperability test bed to support automation and material handling demonstrations, and created a set of equipment performance and EHS documents.
An update on 450mm activities in SEMI Standards
The SEMI Standards program is also making substantial progress towards enabling pilot development and providing a platform for future development work. SEMI has published six standards (Table 1) and is working on 11 draft documents relating to 450mm (Table 2). In addition, SEMI has organized standards task forces for 450mm silicon wafers, physical interfaces and carriers, and assembly and packaging.
The SEMI Standards program is overseeing increasing document development activities for 450mm-related standards, reflecting the increased attention and interest demonstrated by the SEMI Standards volunteers. Industry volunteers who are working on establishing standards on wafer specifications remind us of the original roots of the SEMI Standards program. With mechanical handling wafer, carrier, and load port specifications in place, the industry can cost-effectively continue the research and development of interfaces, processes, materials, and equipment which will be required for semiconductor manufacturing on 450mm wafers.
Specifications for 450mm front-opening unified pods (FOUPs) (SEMI E158-1110) and load ports (SEMI E154-1110) were developed to be used together, and are already available. Also, a specification for the interface between stockers and transport components is published as SEMI E156-0710.
While specifications for circuit-quality 450mm wafers are not yet in development, specifications are published for both mechanical handling wafers (SEMI M74-1108), which are used for R&D and semiconductor equipment design investigation; and single crystal wafers (SEMI M76-0710), which are used for process and metrology equipment R&D. Efforts are currently underway to develop a specification for 450mm polished wafer (Doc 5090).
The single crystal wafers specified in SEMI M76 can also be used to establish the techniques and metrology necessary to support a dimension specification for circuit-quality 450mm wafers. For the 450mm wafer size, edge profile and flatness need to be refined further than what has been used for smaller wafer sizes, and specifications for each of these are addressed by Doc 4588 and Doc 4812.
Figure 1. 450mm activity map.
A specification for a front-opening shipping box (FOSB) has been completed (Doc 4760), along with a specification for a new carrier for 450mm wafers, the Multi-Application Carrier or MAC (Doc 4770). The MAC is focused on silicon manufacturing and processed wafer shipping and is designed to be compatible with both load ports and especially FOUPs, using the same envelope, factory integration, and interoperability interfaces. Both 4760 and 4770 passed technical committee review. Draft Documents 4980 and 4981 modify SEMI E154 and SEMI E158 respectively to provide strong integration between FOUPs, carriers, MACs, and FOSBs. Also, with the completion of the shipping box activity, the next step is for the development of a specification for 450mm wafer shipping system (Doc 5069) that will address materials, dimensions and necessary items related to 450mm wafer shipping system, such as wafer shipping boxes, bags, labels, cushions, secondary containers, pallets, and shipping documentation.
On the assembly and packaging side, the Specification for Tape Frame for 450 mm Wafer, formerly Doc 4815, was recently published as SEMI G88-0211. Meanwhile, document development is in progress for specifications for frame cassettes (Doc 4814) and load ports for frame carriers (Doc 4965).
The expertise required for these documents is diverse, and for these future standards to work together, there must be cooperation across the technical committees sponsoring their development. An Auxiliary document is currently under development that would serve as a guide to how 450mm standards work together (Doc 5108).
The 11 "draft document" standards that are under development in accordance with an open and transparent consensus-based industry-wide process are listed in this chart.
SEMI 450mm Committee and Task Force structure
The current structure for SEMI 450mm activities involves three key technical committees that work together to make sure that the standards developed work effectively together.
- Physical Interfaces & Carriers Committee: Develops specifications to enhance the manufacturing capability of the semiconductor industry, specifically mechanical, electrical, and special equipment specifications; and material movement integration, including substrate support and containment structures.
- Silicon Wafer Committee: Develops standards for commercial silicon wafers, which includes specifications and guides for silicon wafers, test methods for silicon wafer quality and geometry, shipping box related topics, wafer ID related topics, and other issues that support communication between suppliers and customers.
- Assembly & Packaging Committee: Develops specifications to enhance the manufacturing capability of the semiconductor industry as it relates to the packaging and assembly of the semiconductor chip, including the materials, piece parts, and interconnection schemes as well as the total infrastructure for chip to final set system and processes.
With dramatic cost reductions in the semiconductor industry, technology innovations have spurred enormous economic benefits throughout our lifetimes. With a growing consumer class in developing countries such as China and India, this economic progress can continue to fuel average annual growth rates of 8-10%. For over the last decade, sustaining Moore’s Law and industry cost reductions has been supported by highly-refined global collaborative processes such as the ITRS, SEMI standards, and industry consortia. As the global supply chain deals with wafer size transition, pre-competitive collaboration will continue to be the best path towards economic efficiency and industry rationality, and Standards play a major role.
Jonathan Davis is president, Global Semiconductor Business, SEMI, 3081 Zanker Road, San Jose, CA 95134 USA. For more information on SEMI, visit www.semi.org