CEA-Leti Annual Review: IDMs’ top 3 challenges

by Hughes Metras, U.S. development, Leti

June 28, 2011 – Jean-Marc Chery, CTO and EVP of ST Microelectronics, provided the audience at Leti’s 13th Annual Review in Grenoble, France, with a view of the challenges facing IDM companies focused on system-on-chip (SOC) markets. Multimedia convergence, with products ranging from desktops to wireless devices, and the coming cloud computing connecting them, is driving advanced CMOS technology development, he said.

The three primary challenges for IDMs are the transition to FinFET as a probable standard from the 14nm node, the adoption of EUV lithography, and the transition to 450mm wafer size. Concerning this last point, Chery noted that 2009 was the year of crossover between 200mm and 300mm (total wafer production in cm2) and suggested that an equivalent transition from 300mm to 450mm is unlikely before 2025.

He also explained that as far as lithography is concerned, EUV will probably be delayed because of technological hurdles. An intermediate and improved option for 22nm and 20nm nodes may be required, and planar 2D FDSOI could then offer the best incremental solution.


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