Design-dependent semiconductor wafer monitoring developed between UCLA, SRC

June 1, 2011 — Semiconductor Research Corporation (SRC), university-research consortium for semiconductors and related technologies, and UCLA Henry Samueli School of Engineering and Applied Science researchers developed a new method of design-dependent process monitoring for semiconductor wafer manufacturing. They expect the method to save 15% of semiconductor fab costs and boost productivity, potentially increasing per-chip profits by 12%.

The sooner defective wafers and chips are caught in the manufacturing process, the less expensive failure is; catching a defect after a device has been fabbed and packaged is not only more costly, it’s also more difficult to assess root causes.

Improving the design-manufacturing interface is one way to find defects earlier. UCLA and SRC decided to take this a step further, driving design intent into the manufacturing process. Using process monitors on wafer lines tested after initial manufacturing steps, manufacturers could evaluate early die performance and wafer yield estimation. This "pruning approach" can remove defective wafers before they make it though the fab and/or packaging. The collaboration’s data shows nearly 70% of failed chips pruned with less than a 1% yield loss. The approach could offer the most benefit during volume ramp, though results will depend on the design and manufacturing processes

An early version of the method appeared in the International Conference on Computer-Aided Design in 2010.

The notion of design-assisted manufacturing helps avoid wasted resources during the chip fab process, said Puneet Gupta, professor of electrical engineering at UCLA, and SRC alumni student. The goal is to stop production on wafers that will "eventually lose money" because the die will fail. Gupta predicts that cost reductions from the SRC-UCLA idea and other design-assisted manufacturing methods could be "as much as one full technology node." Design information can be "meaningfully and practically" leveraged alongside technological solutions for scaling, added Bill Joyner, SRC director of Computer-Aided Design and Test. The benefit would extend to design houses as well, researchers assert.

Researchers are finalizing results from a 45nm silicon prototype, fine-tuning the method, and will begin industry-level implementation in the next few years.

SRC defines semiconductor industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America’s highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. For more information, visit

Subscribe to Solid State Technology/Advanced Packaging.

Follow Solid State Technology on via editors Pete Singer, and Debra Vogler,

Or join our Facebook group


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.