Rekha Rajaram, George Mirth, Rebecca Mih, Intermolecular Inc., San Jose, CA USA; Barry Chen, Steve Lippy, Trace Hurd, ATMI, Inc., Danbury, CT USA; Kevin McLaughlin, ATMI, Inc., Round Rock, TX USA

Since the inception of Cu/low-k process integration [1], one of the most challenging aspects of process development has been via yield loss, a metric which is in part dependent on post-via etch cleaning. The addition of memory and redundant cores to system-on-chip devices has resulted in both larger die sizes and increasing density. Thus, a system-on-chip (SoC) design at or beyond the 40nm node may have hundreds of millions of unique vias, and over a billion total vias per design [2]. For such devices to have acceptable yield, robust via processes are critical, in particular, the post-via etch cleaning step, which faces a three-fold challenge. The cleaning process must completely remove post-etch residue (hard mask, sidewall residue, via bottom), while inducing only minimal k-value shift in the porous dielectric and also preventing degradation of key metals or composites like Cu, CoWP, Ru, or Ru (Ti). Depending on which integration scheme is used, TiN may or may not be removed during the clean step.

With Intermolecular’s support, and using its High Productivity Combinatorial (HPC) R&D methods, ATMI has worked on development of an advanced family of cleaning formulations for a variety of different applications [3-6].

Post-etch residue is created in vias when multi-step anisotropic plasma-etch recipes interact with novel film stacks and the lithography materials used for patterning. The resulting residues are often a complex polymeric mixture of etch gas and film-stack components. Cleaning, therefore, requires formulations or formulation spaces that effectively remove unique customer- and stack-specific residue without affecting critical stack films. An example specification list is shown in Table 1.

One key barrier to development of successful post-via etch formulations is the metrology used to differentiate the formulation path. In the early research screening phase, residue removal is generally judged by inspection. With the use of scanning electron microscopy (SEM) cross-sections, the traditionally preferred method, one can look for and generally determine coarse levels of acceptable or unacceptable metals and dielectric attack, and judge whether the via stack is clean. But these cross-sectional SEMs limit collection of significant information on the amount of residue present at the bottom of the via, due to difficulty in extracting electrons, and limit the experimenter from rapidly determining which formulations statistically clean this residue most effectively. For our early screening work, we have found that automated top-down SEMs and sampling of larger areas of vias provided insight on effective cleaning of via-bottom residue.

With the use of the combinatorial methods described above, we characterized performance using a multitude of blanket films, including Cu, CuOx, low-k, and hard-mask films, along with patterned wafers. Top-down SEM inspection, combined with software analysis, provided more effective evaluation of the hundreds of formulation experiments enabled by the HPC tools. During later stages of the development cycle, as the formulations and processes improve, it becomes more difficult to discriminate formulation cleaning performance, as there are fewer blocked vias. Significant efforts were made in developing voltage-contrast SEM [7] and electrical test methods [8] that are throughput-matched to the process tools, in order to make finer assessments of process and chemistry choices.

Formulation approach

Post-etch residue removal formulations are complex systems whose components are designed to handle the process requirements outlined in Table 1 while also maintaining stack integrity. With ready access to post-etch patterned wafers and blanket film wafers, our experiments were designed to cover three screening phases (primary, secondary and tertiary).

Figure 1. Formulation screening approach for a post-via etch formulation.

To build a formulation from the ground up, we took a staged approach beginning with a primary screening phase outlined in Fig. 1. In the first stage of this primary screen, we define which subsets of components look most suitable for patterned wafer cleaning, and sort that information with their attack rates for the corresponding metal and dielectric materials. In stage 2, the experiments design-in other key components (complexing agents, inhibitors, passivators, and other miscellaneous agents and additives) to narrow the selection of final candidate components as we seek to meet the designated success criteria. In this secondary screening phase, designs of experiments (DOEs) are performed to optimize formulations and assess process tolerances to find the best-performing candidates.

High-productivity formulation enhancement

Prevention of copper corrosion is a challenge for post-via etch cleaning formulations; this often requires the use of corrosion inhibitors. A recent challenge was to enhance a given formulation’s current capability with respect to its shelf life. To study this effect we needed to make observations of the amount of undercut of underlying copper lines on a customer’s 22nm test via. Subsequently, a reformulation effort was undertaken to upgrade the existing corrosion inhibitor with a more robust molecule demonstrating a longer shelf life.

ATMI identified corrosion inhibitor candidates for reformulation that included classes of antioxidants and passivating agents for copper. Antioxidants prevent copper corrosion by scavenging oxygen in the system, whereas passivating agents often have spare pairs of electrons that can coordinate with the vacant d orbitals in copper [9] and thus form complexes that protect the surface from corrosion. Forty-five molecules were picked out from these categories of materials, and screened as additives to the post-etch clean formulation at multiple concentration levels for low copper etch rate. The reformulation involved building and testing 200 chemical formulations, which were all mixed from stock solutions on the Tempus F-10 platform, using its programmable robotic arms. Formulation composition is input into the tool using a library-based software to automate chemical dispensing; this makes it possible to rapidly screen several multi-component chemistries in a relatively short amount of time. The formulations thus prepared were tested for copper removal on the Tempus F-20 tool using blanket PVD copper films at 50ºC for 30min.

Figure 2. Copper removal by post-via-etch cleaning chemistry with different corrosion inhibitors.

The design requirement for the cleaning chemistry included removal of less than 1Å/min of copper at the operating temperature (Fig. 2). All inhibitors that showed removal rates above the specification limit were weeded out and the list was narrowed to 12 inhibitors. This primary screening from 200 down to 12 candidates took place in less than three weeks.

Secondary screening on the shortlisted corrosion inhibitors involved testing on the customer’s 22nm post-via etch structure and examination of copper undercut using SEM and TEM. Satisfactory cleaning and no copper undercut were obtained by using a combination of two corrosion inhibitors found through the screening method listed above. The enhanced formulation was ready for tertiary testing.

Tertiary screening using electrical testing

Tertiary screening of the top candidate formulations was performed on the F-30 platform. This tool allows for up to 28 site-isolated processes to occur on a single wafer with independent control of process chemistry, process time and stir rate in each cell. FOUP-to-FOUP wafer transfer enables reinsertion from Intermolecular’s fab back to the end user fab for final processing and/or electrical testing.

The final formulation optimization is ideally performed on specific patterned wafers because each user’s integration and film properties tend to be unique. Using the tool, the exact formulation chemistry and process conditions can be tailored to particular needs. Typically, users will supply blanket wafers to re-verify the Cu loss, barrier metal loss, low-k damage and hard mask material changes using their 300mm fab metrology tools, as well as patterned BEOL test wafers designed for electrically quantifying the defectivity and reliability of a particular BEOL integration scheme. The F-30 cells are moveable to allow for optimization at the customers’ die pitch [10].

For the purpose of testing post-via etch formulations, we decided to run fab wafers with two splits. The first DOE was to test variants of the formulation at a fixed temperature, to see which customized solution performed best relative to the fab baseline. Once the best formulation was determined, a further optimization was run to statistically check the process window at three process times and three temperatures, with two repetitions.

Once the DOE splits were decided, the customer test lot was prepared and we performed a split into three groups: 1) a control group of several wafers, which remained in the end user fab’s clean environment for continuation of POR processing; 2) a group to test F-30 particle levels, using a traveler wafer and bare silicon particle monitors; and, 3) split-identified wafers for DOE processing at Intermolecular’s San Jose fab [10]. After processing, the split wafers, the traveler wafer and the bare silicon monitors were combined and returned to the end user’s fab. The particle monitors were checked for contamination and found to be acceptable. Prior to metallization, bare silicon particle monitors were used before and after processing of the split lot, and no additional adders were found as a result of processing [10]. The traveler wafer was rejoined to the POR split, and processed with POR (fab baseline) post-via etch cleaning; the Tempus F-30 split wafers were then rejoined to the lot for POR metallization, copper electroplating, CMP, passivation and aluminum contact processing, before undergoing electrical test.

Testing included several types of via configurations, including Kelvin vias and via-chain test macros where the via and metal lines were the same critical dimension. As mentioned previously, during the later stages of development, the cleaning performance improves and small via chains should yield near 100%. To differentiate these higher-performing chemistries, we tested with the largest via-chain macro, containing over 880,000 vias.

Figure 3. Cumulative distribution function of via resistance for a variety of formulations, processed for two minutes at 50ºC, compared to the fab baseline [10]. Electrical data can be used to guide the best formulation for a particular Cu / low-k film stack.

The split results for the 880K via-chain testing are shown in Fig. 3 and Fig. 4 [10]. In Fig. 4, trial formulations 1-6 were processed inside the F-30 site-isolated cells. The DI water baseline data came from data collected in the large interstitial test areas outside the F-30 cells. Most of these trial results as processed on the Tempus F-30 tool in San Jose compared favorably to the end user’s baseline wafers, which stayed in the fab and were processed with their POR clean. Of the trial formulations, Trials 1 and 2 both have clearly lower mean resistance, as well as much better via resistance distribution and fewer resistance tails. Trial 2 was selected for further study.

Figure 4. Once the best formulation is determined, the process window temperature and time can be statistically validated with electrical measurements. SEM cross-sections were performed as a further validation of this workflow.

Figure 4 shows the result of a process window split for the Trial 2 formulation. The process window was checked with three process times and three process temperatures, and compared to the fab baseline. The best process appeared at 50C, and the results were validated with SEM imaging of the patterned wafers for both the F-30 wafers and wafers run on the high-volume manufacturing (HVM) tool.

With the use of electrical measurements, which can be performed at the end user’s fab test lab, or at HPC-enabled processing centers, we are able to identify and prove-out the best formulation and process window for a customer’s unique integration and film stack.

Conclusion

An advanced materials screening approach using Intermolecular’s combinatorial platforms was used in the challenging development of an advanced Cu/low-k post-etch residue remover. We have demonstrated the primary and secondary screening processes that were used to evaluate a broad range of starting components, as well as binary and ternary mixtures and additives that yielded several promising formulations. Utilizing the F-30 tool and electrical test as a tertiary screening technique, we were able to statistically determine the best formulation and process window for a specific film stack and integration. The HPC methodology dramatically enhances the probability of designing a high-yielding HVM-ready post-etch residue remover and process.

References

1. D. Edelstein, "Cu-Based ULSI On-Chip Wiring Technologies," PEAK June 2008.

2. J. Chen, "GPU Technology Trends and Future Requirements," IEEE IEDM Dec., 2009, Session 1.1.

3. Z. Fresco, et al., "Accelerating Semiconductor R&D with Combinatorial Technology," Solid State Technology, Oct., 2007.

4. D. Canaperi, et.al., "Reducing Time Dependent Line to Line Leakage Following Post CMP Clean," MRS Symp. Proc., Vol. 1249, April, 2010.

5. T. Hurd, et.al., "Using Combinatorial Methods to Accelerate BEOL Cleaning Formulation Development," MRS Symp., April 2010, invited talk.

6. T. Chen, et. al., "Environmentally Benign Cleaning Solutions for Wet-based Semiconductor Processes," 10th Inter. Symp. on Ultra-clean Processing of Semiconductor Surfaces (UCPSS), September, 2010.

7. M. Schmidt, et. al., "New Methodology for Ultra-fast Detection and Reduction of Non-visual Defects at the 90nm Node and Below Using Comprehensive e-test Infrastructure and In-line DualBeam FIB," IEEE ASMC, May 2006.

8. C. Hess, et.al., "High Density Test Structure Array for Accurate Detection and Localization of Soft Fails," Proc. of IEEE International Conference on Microelectronic Test Structures, vol. 21, March 2008.

9. M. M. Antonijevic, M. B. Petrovic, "Copper Corrosion Inhibitors. A Review," Int. J. Electrochem. Sci., 3 (2008) 1-28

10. T. Hurd, et. al., "A Combinatorial Approach to Electrical Qualification of Advanced Post-Etch Dielectric Cleaning Chemistries," SPCC 2011, results to be published.

Acknowledgments

We have utilized software from Smart Imaging Technologies, Inc. for the analysis of via blockages. We thank Larry Dworkin and Nick Dawes of FEI Company for their guidance and support in using the Helios DualBeam system. Helios and DualBeam are trademarks of FEI Company. HPC and Tempus F-20 and Tempus F-30 are trademarks of Intermolecular Inc.

Contact author

Rekha Rajaram is a senior applications engineer at Intermolecular Inc., 3011 N. First St., San Jose, CA 95134 USA; ph.: 408-582-5700; email [email protected]

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