by David K. Lam, chairman, Multibeam Corp.
This guest column summarizes an invited talk by industry veteran, David K. Lam, who will be presenting on complementary e-beam lithography at the Advanced Lithography TechXPOT on Wednesday July 13 at noon. Dr. Lam wrote this column exclusively for Solid State Technology.
July 11, 2011 – For decades, optical lithography has driven the semiconductor industry’s growth by patterning ever-smaller IC features onto silicon wafers. This has enabled the packing of more and more transistors into each chip, increasing its performance and reducing its cost, and expanding market opportunities.
However, optical lithography, based on the 193nm ArF technology to transfer design patterns to wafer, is reaching its limits in resolution. The layers that are extremely costly to pattern with optical lithography ("critical layers") are increasing.
Today, to make logic devices manufacturable at advanced nodes, leading fabs are adopting 1-D gridded layouts, resulting in unidirectional lines with fixed pitch. The 1-D layout approach was first applied to the poly (gate) layer and is now expanding to metal layers. Figure 1 shows that Intel adopted 1-D layout in 2007 when it transitioned to the 45nm technology node.
Figure 1. 1-D gridded layout is the way of the future. (Reference: Kuhn, K., "Variation in 45nm and Implications for 32nm and Beyond" 2009 2nd; International CMOS Variability Conference (2009); Reference: Lammers, D., "Intel Going Vertical for 22nm Transistors" (2011).)
The pitch can then be halved and the line density doubled using well-established techniques known as "pitch division." Pitch division employs CVD and etch equipment – processes and materials commonly used in CMOS fabs. The process can be repeated, without additional use of optical lithography, to quarter the pitch and quadruple line density, as reported by Yaegashi of TEL and shown in Figure 2.
Figure 2. 193i with pitch division results in tighter densities. (Reference: Yaegashi, H., "Important challenge for the extension of Spacer DP process" 2010 International Symposium on Lithography Extensions (2010).)
Following line formation is line "cutting," i.e., breaking line continuity, in the fabrication of the device. Line cuts, which are extremely challenging to pattern with optical lithography because of resolution limits, are a critical layer.
In 2010, Yan Borodovsky of Intel showed a line-cut simulation for a 1-D layout pattern at 20nm half-pitch. Cutting the lines with optical lithography would require quadruple patterning and four masks, as shown in Figure 3. Borodovsky proposes the use of another lithography technology such as EUV with one EUV mask, or e-beam lithography (EBL) with no masks at all, to cut the lines, thus complementing optical lithography. He calls this approach "complementary lithography."
Figure 3. Yan Borodovsky of Intel proposes "complementary lithography." (Reference: Borodovsky, Y., "MPProcessing for MPProcessors", Maskless Lithography and Multibeam Mask Writer Workshop (2010).)
Complementary lithography draws on the strengths of two lithography technologies, working hand-in-hand, to lower the cost of patterning critical layers in logic devices at 20nm half-pitch and beyond, in high-volume manufacturing (HVM).
The most cost-effective way to implement complementary lithography is to combine optical lithography with EBL. The process of transferring IC designs to the wafer entails the following: optical lithography to print unidirectional lines in a pre-defined pitch, pitch division techniques to increase line density, and EBL to cut the lines. EBL is also used to pattern other critical layers, notably contact and via holes. Optical lithography patterns all other layers.
When used to complement optical lithography, EBL is called CEBL, or complementary EBL. CEBL is not next-generation lithography (NGL). Rather, it is limited to cutting lines and holes. By not attempting to pattern all layers, CEBL plays a complementary but crucial role in meeting the industry’s patterning needs at advanced nodes. CEBL also extends the use of current optical lithography technology, tools and infrastructure.
(In the podcast below, Lam further summarizes how complementary e-beam lithography (CEBL), as part of the overall solution "complementary lithography," can overcome the resolution limitations of 193i technology.)
Multibeam’s CEBL technology is optimized for cutting lines and holes to achieve high throughput and low cost of ownership. During my presentation at SEMICON West, I will cover Multibeam’s all-electrostatic approach, multi-column architecture, vector scanning of the shaped beam, and in-process local alignment with column-SEM. Recent results in beam profile simulation and optimum process window will also be presented.
The infrastructure to support complementary lithography exists and is available today. This includes 1-D gridded layout IP and software, optical lithography technology and equipment, optical mask writers and mask shops, pitch division equipment, process and materials, e-beam resists, e-beam wafer defect inspection, EDA tools and yield management software. Some mask-writing EDA and yield software are adapted for CEBL and CEBL tool is under development. This eco-system offers a complete solution that scales far beyond the 20nm node.
David K. Lam received his PhD in engineering from MIT, is chairman of Multibeam and is probably best known for Lam Research (NSDQ: LRCX), which he founded in 1980. Lam uses his experience and expertise to provide guidance to emerging technology enterprises, including Microprobe, Xradia, and Multibeam, 4008 Burton Drive, Santa Clara, CA USA 95054, www.multibeam.com.