FDSOI improves CMOS scalability, speed, power consumption at 11nm

By reducing the active silicon thickness (via the use of ultra-thin silicon on insulator [SOI] wafers), Leti has demonstrated the ability of fully depleted silicon on insulator (FDSOI) technology to improve CMOS scalability down to the 11nm node, together with an associated variability reduction of the electrical characteristics by a factor of two compared to regular technologies. Several Leti teams also have reported good results in competitive drivability.

Leti has demonstrated that switching from bulk 28nm to 20nm FDSOI technology can improve circuit speed by 35% or lower the dissipated power by more than 50% at a given speed, which are among the best gains reported on planar technologies, and highlight the benefits of this FDSOI technology. Since this technology does not require any significant process and design breakthroughs, it can thus be considered as an efficient booster of the planar bulk.

Back-bias effect, enhanced with ultra-thin buried oxide (UTBOX) wafers, appears to be a significant advantage to address both low-power and high-performance applications and is also a way to simplify the multiple-VT schemes, essential for the elaboration of a complete platform.

Non-planar devices, known as FinFET, also appear to be good challengers to bulk technology. While similar gains (in terms of speed and power) can be expected (compared to those reported previously with planar FDSOI devices), the non-planar structure of the device significantly complicates the process integration (especially in the case of low-power technology and the design rules.

Planar FDSOI technology is thus considered by our teams as the best trade off between circuit performance improvement and associated process/design complexity.

Olivier Faynot
is the device group manager at Leti. Contact Faynot at [email protected].

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