Suss MicroTec 3D IC workshop addresses thin wafer handling and testing

July 25, 2011 – At this year’s SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

Eric Beyne of IMEC addressed the technical issues of carrier systems for 3D through-silicon via (TSV) thinning and backside processing, pointing out that right now silicon carriers are favored over glass because: (1) the glass must be CTE matched to silicon over a large temperature range, (2) the high cost of ground to tight TTV specification, and (3) a negative effect on plasma-based post-grinding backside processes due to its low thermal conductivity. After alignment and temporary bonding, Beyne recommends the use of use of in-line metrology to insure bonding integrity before grinding occurs.

Rama Puligadda, division manager for advanced materials R&D for Brewer Science, indicated that their Zonebond room-temperature debonding process is meeting all customer requirements and is moving towards full commercial introduction. The Zonebond process basically uses a 2.5mm ring of adhesive to hold the wafer in place for grinding and backside processing. This allows for easier subsequent debonding. The thin wafers are released from the carrier at room temperature after mounting on a film frame.

Stephen Pateras, product marketing director at Mentor Graphics, pointed out that TSVs can be used to create test access paths so that all BIST resources can be accessed on any device. Pateras also concludes that all EDA players need to support common test access infrastructures since this will be required to stack die from difference sources.

Eric Strid of Cascade Microtech revealed that the company is producing lithographically printed probe cards by MEMS techniques capable of 6


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