Thermal wafer processing for Ni(Pt)Si contacts beyond 45nm

July 12, 2011 — The formation of advanced thin nickel-silicide films poses major challenges as devices integration moves beyond the 45nm technology node. X. Pages et al, Renesas Electronics, explain how optimized low-temperature rapid thermal processing (RTP) annealing schemes address this issue.

It is now widely accepted that for the next technology nodes (beyond 45nm), Ni(Pt)Si will fulfill the requirements set by the industry roadmaps [1]. However, despite the known advantages of nickel silicide layers — low thermal budget, low resistivity, low silicon consumption, compatibility with silicon germanium (SiGe) and silicidation controlled by metal diffusion — downscaling brings many process and integration challenges:

  • Reverse line width effect: Ni atoms are the dominant diffusing species in Ni monosilicide formation. While beneficial for reducing bridging between adjacent metal lines, this property leads to excessive silicidation on very narrow lines [2].
  • Low temperature formation of epitaxial NiSi2: also called spiking, this formation is often observed on strained PMOS structures. In this case, the phase formation sequence differs from the conventional transformation from Ni-rich to Si-rich silicide (Ni2Si – NiSi – NiSi2) such that the epitaxial NiSi2 grows already at relatively low temperatures. NiSi2 formed in this way can be observed as characteristically shaped pyramids protruding into the Si substrate.
  • Uncontrolled NiSi diffusion: this diffusion occurs underneath the gate. Mainly observed on NMOS, this NiSi encroachment (also called piping) is a strong function of the Si crystal orientation under the gate [12], of the thermal stress, and of the RTP1 thermal budget [13].
  • High resistive Ni silicide residual phases formed on narrow lines: Residual Ni2Si can cause an increase of the Rs distribution (measured on a short length scale) when a too low RTP2 thermal budget is applied [7]. Moreover, Ni2Si enhances agglomeration and therefore decreases the thermal stability of the thin NiSi:Pt layers even further.

To address these issues, and because advanced devices require a thinner Ni silicide (i.e., lower RTP1 thermal budget), optimized annealing schemes are mandatory.

An essential requirement for the RTP approach is a repeatable temperature measurement and control such that each wafer experiences an identical temperature/time cycle.  This is to be combined with excellent within-wafer temperature uniformity. The process should guarantee a fast and repeatable anneal temperature for RTP1 as well as for RTP2.

Scaling the silicide process

Typically, Ni silicides are formed by a low temperature anneal (called RTP1), followed by a selective etching of the unreacted Ni, and a high temperature soak anneal (called RTP2). In this conventional two-step sequence, the Ni2Si (or Ni2Si:Pt) phase is formed during RTP1 when the diffusion of Ni is limited. The second (higher) temperature step (RTP2) is performed to convert Ni2Si (or Ni2Si:Pt) into the desired low resistivity NiSi (or Ni(Pt)Si) phase. As Ni is already removed by the selective etch at this stage, no excessive silicidation will take place.

Scaling RTP annealing

At the temperatures required for the RTP1 step, basically two heating methods are available: The substrate is either heated by lamp radiation, as in conventional lamp-heated RTA systems, or by placing the wafer on a hot susceptor kept at process temperature. In both heating methods there are several disadvantages: in lamp-heated systems, silicon is basically transparent for infrared radiation, which makes it difficult to design a reliable temperature control system. Standard hot-susceptor systems rely on heat conduction through a thin gas layer present between the wafer and the susceptor. As the heat conduction through gas is inversely proportional to the wafer-susceptor distance, any initial bow and/or warp of the wafer will have a major impact on local heat transfer, and therefore will affect the temperature uniformity.



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