August 4, 2011 — Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC’s major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.

Hot spots create charge losses in stacked chips. Stacking is nice, but if it creates memory losses, it cannot serve the industry, Deferm points out. Heat-spreading through silicon vias may be the answer to this problem. SEMICON West allows imec to bring problem resolutions like this to the design community.

For semiconductor device structures, scaling always has its limits. To get around that, imec developed an implant-free silicon germanium (SiGe) quantum well device. Selective epitaxial growth allows reduced lateral resistance. The channel control is much better, and the structure is scalable, but developments are still ongoing, especially on the PMOS/NMOS interaction.

In memory activities, imec is working on resistive RAM (RRAM) endurance (number of cycles) and materials, and new materials for the metal insulator/metal capacitor for DRAM to reduce leakage. The goal is smaller, denser memory with the same kind of capacity as larger generations.

Deferm also speaks about the lithography tool ASML delivered to imec in Marchl. They are using it for EUV litho exposures and a laser-assisted discharge plasma (LDP) source. These trials are headed for 60 WPH on the tool by 2012. Imec also is working on mask cleaning for EUV.

Wrapping up his talk, Deferm covers industry collaborations in 450mm production tool development, 3D integration, and new devices. Big equipment suppliers having to "do it all" in areas of new technologies, such as EUV and 450mm, want help from IDMs sharing the burden. Collaborations in 3D packaging is more related to applications than economics, and therefore collaborations are different. FinFETs and other new device architectures are only going to be used if neccessary, Deferm predicts, so it will come later than expected.