August 10, 2011 – Post-22nm and below, the industry is going to fully depleted structures, either FinFETs or fully-depleted planar SOI (FDSOI), explained Steve Longoria, SVP, global strategic business development at Soitec, in an interview at SEMICON West 2011. Although Soitec supplies wafers for both structures, the company has introduced a new wafer — extreme SOI — with a thin buried oxide that is used for planar FDSOI. According to an IC Knowledge paper cited by Longoria during the interview, the new technology delivers superior power performance and is cost-competitive with bulk technology. All the major fabless companies and foundries have initiated programs to evaluate the technology, he noted, which Soitec believes is an alternative for 22nm and below.

In a partnership with IBM and ARM, the company was able to demonstrate two different variants: a 30% performance advantage at the same voltage, or a 40% power savings at the same performance. The company leveraged its Smart Cut technology to build the thin buried oxide, and is working with its partners to develop the transistor on top of it. According to Longoria, the development is straightforward because it’s a continuation of a planar transistor. "So it’s evolutionary and straightforward from both a process design standpoint and a manufacturing standpoint," he said. "It’s a much lower risk in the industry for both the designer and the manufacturers than the alternatives."

The company is producing prototypes of extreme SOI now, and providing manufacturing samples on the order of thousands of wafers a month to all the development facilities. "We are in position [between the company’s factories in Singapore and France] to be fully qualified by the end of this year, and our close partnership with SEH in Japan will enable millions of wafers to be supplied over the next couple years," reported Longoria. He said the company is well positioned to meet both the quality and specifications and the volume manufacturing with FDSOI or extreme SOI going forward. "Research suggests we can thin the buried oxide down even more and have scalability well below 14nm, maybe even 11nm — enabling scaling of a planar device, which is going to put the industry in a position to move even faster."