August 9, 2011 – As IC manufacturers go from 28nm to more advanced nodes, they also become more aggressive with strain engineering, explains Jeff Hebb, VP of laser product marketing at Ultratech, in a video interview with Solid State Technology at SEMICON West 2011. SiGe, for example, is introduced into the channel of PMOS transistors to get better performance as the industry goes from 28nm, to 20nm and then to 14nm.
"For millisecond annealing to be compatible with aggressive strain engineering, you cannot introduce extra wafer warpage," said Hebb, "because this introduces photolithography overlay errors." The company’s new LSA system (LSA101) uses shorter dwell times so that dislocations in the wafer do not have time to form and nucleate. On a macro scale, this means the wafer warps much less at the shorter dwell times so it is possible to maintain higher temperatures during millisecond laser annealing. The company’s LSA101 system, with a reduced dwell time of 200