Alchimer TSV barrier-layer film shows 100% deposition coverage

September 6, 2011 — Alchimer’s AquiVia film-deposition technology promises to cut fill deposition times and cost even with complex through-silicon via (TSV) 3D packaging structures. The product targets TSV ramp-up at production levels, according to the company.

The AquiVia TSV barrier-layer process provides uniform, 100% step coverage over complex silicon topography, including high-aspect-ratio vias with scalloped walls. Existing TSV etch technologies tend to create scalloping, steps, and other surface features that challenge subsequent film deposition coverage, said Claudio Truzzi, Alchimer chief technical officer (CTO), noting that vacuum-based deposition processes have failed to create high-quality barrier layers, "especially in deep, small-diameter vias with aspect ratios of 10:1 and beyond." The AquiVia barrier films demonstrate 100% coverage on sides and bottom of vias, even with stair-step patterns and scalloping.

The improved barrier layer, one of the bottom-most elements in the TSV film stack, enables subsequent depositions to be completed in less time and at lower cost, according to Alchimer. The coverage also eliminates certain performance and reliability problems that can occur during subsequent seed-layer and fill deposition, such as "electromigration, poor fill results, and high-resistance pathways in interconnect circuits," said Truzzi.

AquiVia Barrier and Alchimer wet deposition products offer conformality, step coverage and purity that reduce costs and improve performance over PVD, CVD, or other dry processes, according to the company.

Alchimer will be exhibiting with their Taiwanese partner, Kromax, at SEMICON Taiwan Booth 672, Sept. 7-9, 2011. Alchimer will present at a DigiTimes workshop on optimum 3D TSV structures and processes, on the afternoon of Sept. 7th at the Grand Hyatt, Taipei.

Alchimer makes chemical formulations, processes and IP for the deposition of nanometric films used in a variety of microelectronic and MEMS applications, including wafer-level interconnects and TSVs for 3D packaging. Visit

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