September 19, 2011 – At SEMICON Taiwan 2011, the SiP Global Summit consisted of forums on 3D IC technology, 3D IC test and embedded substrates. In the 3D IC technology forum leaders representing key segments of the eco-system shared their experiences in 2.5D and 3D ICs with a focus on technology roadmaps, supply chain manufacturing readiness, business models, and standardization.

Victor Peng, SVP at Xilinx, updated the audience on the ongoing commercialization of the company’s 7V2000T FPGA with "stacked silicon interconnect technology" (SSIT). The FPGA 28nm slices are assembled "side by side" on a silicon interposer with 65nm interconnect wiring. They found the interposer was an excellent way to handle the 28nm chip low-k fragility. Chip fabrication, interposer fabrication, and bumping are being done by TSMC; chip bumping and module assembly are being done by Amkor. Peng reports that they are on schedule for sampling in calendar year 2011. He also noted that Xilinx "believes in full 3D IC stacking (no interposer)" but that it will take a little longer for that technology to become standardized in the infrastructure.

Takayuki Watanabe, VP of Elpida‘s TSV packaging development group, described the company’s memory TSV production flow and how its 16Gb DDR3 module — two stacks, each stack consists of four low-power, 2Gb DDR3 SDRAMs fitted to a single interface chip using TSV — occupies 70% less space (11mm