November 1, 2011 — 2.5D, 3D and Beyond – Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D (through-silicon vias [TSV]) and 2.5D packaging (side-by-side die interconnection on a silicon interposer) moving from roadmap to factory production.

Large, vertically integrated and volume-driven companies are using these advanced packaging technologies for new products, like stacked memory, or ASIC, ASSP, FPGA, and standard product designs. Opportunities include solving latency and bandwidth issues in high-end systems and combining different silicon processes or disparate functions such as MEMS, image sensors, and optics.

MEPTEC