FinFETs for sub-20nm SoCs

IEDM 2011 slideshow
Graphene devices in a 200mm fab
Hynix pushes NAND limits
FinFETs for sub-20nm SoCs
Mapping FinFET carrier profiles in 3D
Hollow copper 3D TSVs

Intel rocked the IC world earlier this summer when it showed off its 3D "trigate" transistor structure for 22nm ICs. It intentionally avoided the term "FinFET" which generally describes any multigate fin-based architecture. At IEDM, there are about a dozen papers doing something with various sub-20nm FinFET architectures. In this one, researchers from GlobalFoundries are describing circuit and device interactions in fully depleted FinFETs for =14nm targeting future SoC applications.

[Paper #4.1: Architecting Advanced Technologies for 14nm and Beyond with 3D FinFET Transistors for the Future SoC Applications" (Invited), A. Keshavarzi, D. Somasekhar, M. Rashed, A. Khakifirooz, K. Maitra, R. Miller, S. Ahmed, A. Knorr, C-H. Shaw, S. Banna, R. Augur, S. Luning, M-R. Lin, S. Vekatesan, S. Kengeri, G. Bartlett, GlobalFoundries]

FinFETs patterned by sidewall image transfer.


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