Hynix pushes NAND limits

IEDM 2011 slideshow
Graphene devices in a 200mm fab
Hynix pushes NAND limits
FinFETs for sub-20nm SoCs
Mapping FinFET carrier profiles in 3D
Hollow copper 3D TSVs

The beat goes on for NAND flash, as Hynix shows in an IEDM paper a "middle-1Xnm" NAND flash memory cell. Several issues had to be addressed: how to pattern the device (solution: quad-spacer patterning with ArF immersion), CG poly filling/interference (solution: FG slimming), and charge loss/UV Vt decrease (solution: airgap and N&plusmn1 WL bias control).

[Paper #9.1: A Middle-1X nm NAND Flash Memory Cell (M1X-NAND) with Highly Manufacturable Integration Technologies," J. Hwang, J. Seo, Y. Lee, S. Park, J. Leem, J. Kim, T. Hong, S. Jeong, K. Lee, H. Heo, H. Lee, P. Jang, K. Park, M. Lee, S. Baik, J. Kim, H. Kkang, M. Jang, J. Lee, G. Cho, J. Lee B. Lee H. Jang, S. Park, J. Kim, S. Lee, S. Aritome, S. Hong, S. Park, Hynix Semiconductor Inc.]

Cross-section TEM view of the cell: (a) along WL direction, (b) along BL direction. The CGs are well-patterend with middle-1Xnm half-pitch.


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