November 16, 2011 — ICs developed at advanced technology nodes of 65nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues, as devices and structures get smaller and smaller. These factors make yield management a big challenge for wafer fabs. Data failure analysis (DFA), electrical failure analysis (EFA), and physical failure analysis (PFA) are three important methods for yield management. DFA is to analyze field failure data such as correctness and performance. EFA and PFA are to identify the physical location of the failure, find this physical failure in the chip, and then link it to a process step to fix in-line problems. However, traditional wafer-level EFA and PFA methods on advanced technology products are no longer sufficient. It is important to trace the implementation of the solution to ensure that no side effects from these actions have created new failures, and to make sure that the failure will not appear again.

Overview of yield management in fabrication

Yield management in the foundry involves many players. Technical development, process integration engineers, inline process engineers, and reliability engineers all have responsibility for meeting the expected yield. Technical development engineers in charge of process development and optimization give technical and design support for inline production wafer manufacturing. Process integration engineers monitor inline defect sources for defect reduction and control the quality of wafer acceptance test (WAT) results. Inline process engineers assure the machines are working smoothly and improve the process margin. Reliability engineers monitor inline production wafers reliability performance. But inline process always has variations, which will induce wafer low yield or reliability/quality issues. When the customer or test feedback finds a yield issue, the product engineer is in charge of yield analysis and will apply DFA, EFA and PFA. The traditional physical and electrical failure analysis is (EFA and PFA) shown in Fig. 1.

Figure 1. Traditional EFA and PFA methods.

When logic or memory products fail, DC test data analysis is the first step. From this we can determine whether bad dice have different DC currents and waveforms from good ones, which helps with fault localization. When the outliers are found, techniques to identify