At 22nm, leave chip layout to the experts

December 28, 2011 — The transition from 32nm to 22nm silicon will have a major impact on the semiconductor design community. The most obvious is the increase in process variation. This affects timing, but more importantly, it affects power. Because of this, we are seeing a dramatic increase in the 22nm process design rules. More and more design teams will decide to leave the IC layout portion of the design to the experts.

The effects of 22nm on the EDA vendors will be a combination of opportunity and shrinking IC layout seat count. Although the new design rules moving toward structured silicon reduce the need for optical proximity correction (OPC) tools, the move to double-patterning lithography raises new challenges for OPC tools, resulting in overall market growth. The variation problems will also drive the demand for design-for-yield (DFY) tools. The new variation challenges require that IC place-and-route tools actively ensure the robustness of the final layout, therefore, growing the IC layout market for those tools that keep up with the 22nm challenge.

This shift in responsibility won


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