December 7, 2011 — Arteris Inc., network-on-chip (NoC) interconnect IP company, will incorporate its FlexNoC NoC interconnect IP into an SoC die on silicon interposer test chip with Taiwan Semiconductor Manufacturing Company (TSMC). TSMC recently approved additional spending on advanced packaging tech.
"TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges," said Suk Lee, director of design infrastructure marketing at TSMC.
Arteris’s FlexNoC NOC interconnect IP is physically implemented as a distributed network of small design elements within a SoC floorplan. FlexNoC addresses bandwidth, latency, and quality of service (QoS) requirements introduced with wide data paths.
Arteris is a TSMC Open Innovation Platform Partner and a participant in TSMC’s Reference Flows 11.0 and 12.0.
Arteris Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. More information can be found at www.arteris.com.