December 29, 2011 – At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC‘s Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC — claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

Yu told the audience of more than 200 that sharing the fabrication process with OSATs is not the preferred option for TSMC, because "the risk for the customer is too high […] therefore we [TSMC] will take full responsibility and accept full risk." TSMC is proposing that such one stop shopping will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing: "This is a new ballgame; the old ways of doing business are out of date for this new technology." On rumors that TSMC is currently working with only a handful of 2.5D/3D customers (including Xilinx); he indicated that "new customers will have only the integrated solution proposal […] some, but not all of them [customers] want us to work with other partners, but many like our new approach very much."

Certainly with customer Xilinx being first to enter the 2.5D market space, TSMC appears ahead of the rest of the foundries in this regard. Ivo Bolsens, VP and CTO of Xilinx detailed the company’s Virtex 2000T FPGA product which he claims delivers 4