July 26, 2011 – Despite the evolving confusion with other "3D" technologies, 3D IC integration has been making significant commercial strides in the last 12 months because many think it will ultimately be the low-cost, high-performance solution.

Care should be taken when searching the 3D literature these days because confusion has arisen in the news media when discussing 3D integration (with through-silicon vias), 3D packaging (i.e. package-on-package), 3D for TV (stereoscopic 3D) and "3D IC" (the latest name for Intel’s finFET transistor structure).

When examining the commercial introduction of 3D integration (with TSV) one must remember that ultimately the acceptance of new technology introductions always come down to economics and ROI. When determining the valuse of 3D integration one must compare it to the costs of the manufacturing facilities for the "next node" . Fab costs for the 22nm node are expected to approach $6B, leaving few logic or memory IDMs or foundries who can afford such costs.

Fab start-up cost comparison in US $M. (Source: GlobalFoundries)

For example, one can see that the number of players in each succeeding generation of logic node has been diminishing rapidly.

(Source: IBS, at SEMI Industry Strategy Symposium [ISS], Jan. 2010)

In addition, with design costs approaching $100 MM at the 22 node, the production volume needed to absorb design NRE keeps increasing, making use of that node limited to high volume products that can absorb such costs.

(Source: Gartner)

Thus, it is the conclusion of many practitioners that next generaton designs will move to 3D IC with TSV because they will be the low cost, increased performance solution.

Certainly, a look at the headlines since last June generated by some of the major players led by Xilinx, TSMC, Elpida and Samsung, clearly show 3D integration is entering the commercialization stage. How far it will go towards becoming a commodity technology will depend on the accuracy of the aforementioned economic considerations.