SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

July 14, 2011 — Sitaram Arkalgud, director of interconnect at SEMATECH, co-moderated a session on 3D perspectives and development of the infrastructure during the 3D TechXPOT session at SEMICON West ("3D in the Deep Submicron Era," July 13 at 1:50PM]).

Arkalgud discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. The figure is a summary of SEMATECH’s results from its survey on gaps in the via-mid ecosystem.

In the podcast, Arkalgud reports on the efforts that have gone into developing a kind of "dashboard" for standardization efforts being undertaken by SEMATECH’s 3D Enablement Center, SEMI, and other standards bodies/organizations such as IEEE, JEDEC, and Si2. He also discussed the anticipated timeline for 3D TSV applications and volume manufacturing (see the chart).

Chart. 3D TSV outlook. SOURCE: SEMATECH
– 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs – High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; 2011-2014 timeframe – Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test – Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below
Gaps in Standards and Specifications EDA Exchange Formats: Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis Reliability: Reliability test methods Test: DFT test access architecture Inspection/metrology: TSV voids, defect mapping, microbump inspection and coplanarity Chip Interface: Stackable memory pin assignment; Stackable memory physical pinout TSV: Keep out area, fill materials, dimensions Thin wafer handling: Universal thin wafer carrier	Technology Development and Cost Reduction Reliability: Criteria; Test methods; ESD Temporary bond/debond cost reduction: Materials and release mechanisms cost reduction; Equipment cost reduction TSV: Keep out distance/area Microbumping and bonding: Pad metallurgy and layer thickness; Bump metallurgy Inspection/metrology: Microbump inspection and coplanarity; TSV voids; BWP voids Test: Probing microbumps cost reduction

Chart. 3D TSV outlook. SOURCE: SEMATECH

– 12 companies surveyed Aug-Sep 2010: IDMs, foundries, fabless, OSATs
– High density via-mid applications including interposers, heterogeneous stacking, logic on logic, memory on memory; 2011-2014 timeframe
– Addresses all aspects of via-mid: wafer processing, assembly, reliability, inspection/metrology, design, test
– Highest priorities for heterogeneous stacking (e.g., wide IO DRAM) shown below

Gaps in Standards and Specifications
EDA Exchange Formats: Partitioning and floorplanning; Logic verification; Power/Signal integrity analysis; Thermal analysis flow; Stress analysis flow; Physical verification; Timing analysis

Reliability: Reliability test methods

Test: DFT test access architecture

Inspection/metrology: TSV voids, defect mapping, microbump inspection and coplanarity

Chip Interface: Stackable memory pin assignment; Stackable memory physical pinout

TSV: Keep out area, fill materials, dimensions

Thin wafer handling: Universal thin wafer carrier

Technology Development and Cost Reduction
Reliability: Criteria; Test methods; ESD

Temporary bond/debond cost reduction: Materials and release mechanisms cost reduction; Equipment cost reduction

TSV: Keep out distance/area

Microbumping and bonding: Pad metallurgy and layer thickness; Bump metallurgy

Inspection/metrology: Microbump inspection and coplanarity; TSV voids; BWP voids

Test: Probing microbumps cost reduction

SEMATECH has been busy at SEMICON West 2011:

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