Via-last 3D packaging and interposer metallization costs chat

July 21, 2011 — Steve Lerner, CEO of Alchimer, discusses the company’s latest suite of through silicon via (TSV) technologies in a podcast interview at SEMICON West 2011.

Earlier this year, Alchimer announced a new wet-deposition process, AquiVantage (see figure), that grows interconnect layers for interposer redistribution layers (RDLs) and enhances via-last backside wafer interconnects. The new process provides concurrent wet deposition of TSV and front-side isolation, barrier, and copper fill/RDL, while eliminating chemical mechanical polishing (CMP) and dry deposition steps. It also supports smaller vias with higher aspect ratios. On the backside, the process allows selective maskless growth of the on-silicon isolation layer, completely eliminating an entire expose/develop/etch/clean lithography-process cycle. Lerner discusses how the new technology reduces costs. "It’s an agnostic platform that can be transferred to existing assets rather than constructing new equipment," said Lerner.

Figure. Top part of a SEM cross-section highlighting the concurrent growth of TSV and RDL isolation and barrier, as well as the concurrent TSV Cu fill and RDL Cu seed deposition. The SEM inlens method used for this photo shows a high contrast between the polymer isolation and the metallic materials.

According to company, overall, interposer cost savings of more than 50% are achievable with the new process. The technology also accommodates thicker wafers, eliminating the need for wafer carriers and allows for highly scalloped via structures and faster etching times.

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