January 2, 2012 — As the semiconductor industry moves closer to starting 20nm logic device production, 2012 will be a period of fine-tuning and process improvement. To enable wafer process integration, production-quality photomasks must be available 18 months to 2 years ahead of volume wafer production ramp.

With the first 20nm test chips coming out now, the 20nm mask production toolkit and materials have been selected and installed at the leading mask houses, and the 20nm mask process has been developed. The task for 2012 is to improve mask yield and cycle time before volume wafer manufacturing begins.

20nm production will be done with 193nm argon-fluoride (ArF) immersion lithography. The workhorse lithography technologies will be double-patterning (DPT), source mask optimization (SMO), or some combination of the two.

Mask patterns are already complex due to the pervasive use of OPC, and SMO — which simultaneously optimizes both source and mask designs to improve wafer print accuracy — further increases pattern complexity. SMO also challenges resolution and critical dimension (CD) accuracy beyond current limits.

The above considerations affect the mask in two ways. First, pattern complexity drives electron beam shot count, which in turn determines mask write time; mask write times will increase. Second, the mask blank and resist materials have been changed to include thinner resists, thinner hard mask and thinner absorber layer with adjusted composition. Moving from chrome to molybdenum silicide absorbers produced better CD quality, printing results, and mask durability at 32nm. That evolution will continue at 20nm, although we haven’t seen the end of mask durability issues.

Along with these mask blank and resist changes, new demands will be placed on CD metrology. For example, instead of measuring a one-dimensional CD, 2D shape metrology and even sidewall metrology will become commonplace. Mask inspection will also become more demanding because pattern complexity drives mask inspection time and challenges inspection tool resolution.

Improved double-patterning. Double-patterning offers relaxed pitch and pattern complexity compared to single patterning, but it requires strict pattern placement and CD accuracy. This will challenge mask writing tool and metrology accuracy.

Fortunately, a number of new correction methods will help with these issues. Pattern placement accuracy can be improved with charge effect compensation and e-beam drift correction. Beyond e-beam control, pattern loading compensation can improve CD accuracy regardless of the neighborhood around a feature.

Historically, pattern placement accuracy was determined by measuring locations of fiducial marks placed outside the main circuit. A key improvement in placement metrology is to measure in-die features, which are much smaller than typical fiducials and therefore require better metrology tool resolution and accuracy.

As 20nm manufacturing matures, some wafer manufacturers may introduce EUV lithography to gain experience with the technology. But widespread adoption will not occur until 14nm or later, after a reliable, powerful EUV source becomes available.

At the moment, 28nm technology is entering volume production at the leading foundries. In two or three years, 20nm will be in the same position, and its successful introduction will be enabled in part by the mask technology work in 2012.

Franklin Kalk is CTO of Toppan Photomasks.

This article is part 9 of a series of 22nm forecasts from Solid State Technology contributors.

Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner

Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA

Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys

Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S

Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International

Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America

Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech

Part 8: Startups pave the way to CMP at 22nm by Michael A. Fury, Techcet Group

Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group