January 2, 2012 — Defect control at 22nm is a critical focus for chemical mechanical polishing (CMP). Slurry manufacturers have worked hard to deliver stable suspensions that resist agglomeration in manufacturing, storage and shipment. Metrology suppliers have developed the ability to measure particle size distribution offline in undiluted slurry samples, emphasizing the large particle tail associated with scratch defects. In the latest advancement, a Silicon Valley startup — yes, they still exist and still bring valuable innovations to the party — called Vantage Technology Corporation, has introduced a non-destructive real-time online measure of the large particle tail using a 15 ml/min slipstream of slurry flowing in the distribution system or into each polisher at POU. The additional level of defect protection over periodic slurry sampling remains to be quantified, but at least now you can measure in the slurry what you are trying to control on the wafer.
But slurry agglomerates are not the sole source of polishing defects. CMP is a dynamic process that generates chemical by-products and requires pad conditioning to maintain removal rate and planarity control. Conditioner manufacturers have done a commendable job reducing diamond fallout in conditioners that still use grit, and eliminating it altogether in conditioners that use DLC coatings over a micro-replicated engineered ceramic surface. The fact remains, however, that conditioning intentionally creates pad debris that itself is a source of polishing defects. The promise of conditioning-free CMP pads remains unfulfilled. Removing the pad debris as it is created is the value proposition of a solution developed by another startup company, Confluence LLC. Having the pad conditioner clean up after itself is good manners, if nothing else. Vacuuming up the pad debris is not selective; spent slurry and chemical by-products are removed too. As a result, new slurry goes straight to the wafer without being mixed with spent slurry. This has the unexpected benefit of shifting the process steady state from a dilution regime to a replacement regime; the wafer is effectively seeing undiluted fresh slurry with each rotation of the platen. The benefit is higher removal rates, thus higher productivity, and lower slurry flow rates, thus lower cost, all resulting from a direct approach to removing pad debris at its source.
With an ITRS critical scratch length of 20nm, comparable to the size of particles that do most of the polishing, CMP engineers are lucky that startups are still producing creative solutions to tackle these issues.
Michael A. Fury, PhD., is director & senior materials analyst of Techcet Group.
This article is part 8 of a series of 22nm forecasts from Solid State Technology contributors.
Part 1: Semiconductor process technology challenges at 22nm by Dean Freeman, Gartner
Part 2: At 22nm, leave chip layout to the experts by Gary Smith, Gary Smith EDA
Part 3: Focus on first order effects at 22nm by Howard Ko, Synopsys
Part 4: Mask-wafer double simulation: A new lithography requirement at 22nm by Aki Fujimura, D2S
Part 5: 22nm requires foundry-to-packaging-house cooperation by E. Jan Vardaman, TechSearch International
Part 6: Strained silicon and HKMG take the stage at 22nm by Mohith Verghese, ASM America
Part 7: Will 22nm need a mid-node? by Art Zafiropoulo, Ultratech
Part 9: 20nm mask technology relies on SMO and DPT by Franklin Kalk, Toppan Photomasks
Part 10: 3D integration key to 22nm semiconductor devices by Paul Lindner, EV Group