UltraFlat wafer-level semiconductor test process creates permanent PCB flatness

January 9, 2012 — Multitest, semiconductor test equipment provider, qualified its UltraFlat process for high parallel vertical probe card tests. UltraFlat provides permanent overall PCB flatness for better wafer-level test.

For applications such as DDR3 memory, board flatness is crucial at wafer-level testing. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Additionally, flatter PCBs require less compliance from the probe interface and reduce interface wear.

UltraFlat is based on PCB stack up engineering and PCB construction technologies, allowing for a very tight overall flatness tolerance to be maintained by removing bows/twists in the PCB. The technique creates a permanent overall flatness, unlike baking techniques that are temporary, Multitest reports.

With UltraFlat, Multitest typically is able to comply with bow/twist requirements of 1.0%.

Multitest manufactures test handlers, contactors, and ATE printed circuit boards for semiconductor test. For more information, please visit www.multitest.com/pcb.

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