March 6, 2012 — Imec has released an early-version process development kit (PDK) for 14nm logic semiconductor chips, targeting readiness for numerous new key technologies, such as FinFET architectures and EUV lithography (EUVL).
The PDK anticipates the introduction of FinFET transistors at the 14nm node, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.
This first 14nm PDK contains all elements for design assessment of the 14nm node through device compact models, parasitic extraction, design rules, parameterized cells (pcells), and basic logic cells.
imec’s partners can access the PDK, which will be followed by incremental updates. Imec and its partners are developing a 14nm test chip to be released in H2 2012 using this PDK. This chip will allow testing the device-, interconnect-, process- and litho assumptions, as well as performance and power of circuits implemented at the tight area budgets of the 14nm node.
The 14nm PDK was developed within imec’s INSITE program and its collaborative affiliation partners. INSITE focuses on very leading-edge technologies to plan for more advanced systems and applications of the future. Imec performs world-leading research in nanoelectronics. Further information on imec can be found at www.imec.be.