Synopsys launches 3D packaging EDA line-up

March 26, 2012 – PRNewswire — Semiconductor design/manufacturing software supplier Synopsys Inc. (Nasdaq:SNPS) is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. The 3D-IC initiative will bring in leading IC design and manufacturing companies to work with Synopsys on a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

The 3D-IC technology initiative will focus on design requirements of multiple die to be stacked vertically, or in a side-by-side "2.5D" configuration on a silicon interposer. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Thermal mismatch can lead to silicon deformation and hurt transistor performance. Through-silicon vias (TSV), microbumps and other solder bumps produce a permanent stress in their silicon zone. Synopsys’ Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks. Semiconductor companies, such as foundries, then use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.

Synopsys’ EDA offering in the 3D-IC initiative includes DFTMAX design-for-test test automation; DesignWare STAR Memory System IP for integrated memory test, diagnosis and repair; IC Compiler for place-and-route support; StarRC Ultra parasitic extraction support for TSV, microbump, interposer RDL and signal routing metal; HSPICE and CustomSim circuit simulation; PrimeRail IR-drop and EM analysis; IC Validator for DRC for microbumps and TSVs and LVS connectivity checking between stacked die; Galaxy Custom Designer for custom edits to silicon interposer RDL, signal routing and power mesh; and Sentaurus Interconnect thermo-mechanical stress analysis.

The Synopsys 3D-IC solution is available now in beta and is expected to be in production in calendar Q2 of 2012. Synopsys’ 3D-IC solution will be highlighted at the Synopsys User Group (SNUG) Silicon Valley event on March 26-28, 2012.

Synopsys, Inc. (Nasdaq: SNPS) provides electronic design automation (EDA) for semiconductor design, verification and manufacturing. For more information on Synopsys’ 3D-IC solution, please visit: http://www.synopsys.com/3D-IC.

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