Intel, Xilinx fund chip design software company Oasys

April 12, 2012 — Chip design software start-up Oasys Design Systems added Intel Capital and Xilinx to its investors in a Series B round. Intel Capital is Intel’s global investment organization. Xilinx is a top fabless semiconductor company that makes programmable chips. Oasys will use the funds to expand R&D and build a global support structure.

The company developed Chip Synthesis, challenging the traditional synthesis methods for IC design and implementation, aiming for better chip-level synthesis. Oasys’ RealTime Designer performs physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. Its RTL placement approach eliminates unending design closure iterations between synthesis and layout.

Texas Instruments, Qualcomm and Xilinx are among RealTime Designer users. “Xilinx has licensed Oasys technology and achieved excellent results across a wide range of designs,” said Salil Raje, vice president of Software and IP Product Development at Xilinx. “Oasys’ technology has the potential to positively impact the design flow for VLSI chip implementation,” added Shishpal Rawat, director, Business Enabling Programs at Design Technology Solutions Group, Intel.

“With tapeouts at 45- and 28-nanometer process nodes, Realtime Designer is the proven synthesis solution offering substantial runtime and capacity advantages for some of the world’s most complex designs,” remarked Paul van Besouw, Oasys’ president and CEO.

In 2011, Oasys enhanced its Chip Synthesis platform by adding design for test (DFT) capabilities and support for chip-level power design, further extending the fast speed and high capacity of RealTime Designer.  These additional features completed the fully integrated Chip Synthesis design flow.

Oasys Design System offers a logic IC design platform called Chip Synthesis that can take the RTL for today’s largest chips, along with the floorplan and produce placed gates that meet the design constraints. Learn more at http://www.oasys-ds.com/.

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