MEMS and microelectronics undergo contactless delamination tests at Georgia Tech

April 13, 2012 — Georgia Institute of Technology researchers have used magnetic repulsion force as a fixtureless, noncontact tool for measuring the adhesion strength between thin films in microelectronic devices, photovoltaic cells, and micro electro mechanical systems (MEMS).

The magnetically actuated peel test (MAPT) could help electronics engineers understand and predict delamination/debonding, and improve resistance to thermal and mechanical stresses.

Figure 1. A specimen fabricated for the magnetically actuated peel test (MAPT). The silver cylinder in the center is the permanent magnet. SOURCE: Thin Solid Films.

The right materials will enable smaller, higher-performance, reliable electronic devices, said Suresh Sitaraman, a professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “This technique would help manufacturers know that their products will meet reliability requirements, and provide designers with the information they need to choose the right materials to meet future design specifications over the lifetimes of devices.”

Thermal stresses occur when different layers within an electronic device have mismatched coefficients of thermal expansion (CTE), and will cause layers to separate. Researchers want to know if these layers will separate as the device is used over time, eventually causing failure, said Sitaraman.

Figure 2. Georgia Tech School of Mechanical Engineering professor Suresh Sitaraman (left) and doctoral student Gregory Ostrowicki (right) examine a specimen (seen in Figure 1) fabricated for the magnetically actuated peel test (MAPT). SOURCE: Thin Solid Films.

Sitaraman and doctoral student Gregory Ostrowicki have used their technique to measure the adhesion strength between layers of copper conductor and silicon dioxide (SiO2) insulator. They also plan to use it to study fatigue cycling failure, which occurs over time as the interface between layers is repeatedly placed under stress. The technique may also be used to study adhesion between layers in photovoltaic systems and in MEMS devices.

The Georgia Tech researchers used standard microelectronic fabrication techniques to grow layers of thin films that they want to evaluate on a silicon wafer. At the center of each sample, they bonded a tiny permanent magnet made of nickel-plated neodymium (NdFeB), connected to three ribbons of thin-film copper grown atop silicon dioxide on a silicon wafer.

The sample was then placed into a test station comprising an electromagnet below the sample and an optical profiler above. Voltage supplied to the electromagnet was increased over time, creating a repulsive force between the like magnetic poles. Pulled upward by the repulsive force on the permanent magnet, the copper ribbons stretched until they finally delaminated.

With data from the optical profiler and knowledge of the magnetic field strength, the researchers can provide an accurate measure of the force required to delaminate the sample. The magnetic actuation has the advantage of providing easily controlled force consistently perpendicular to the silicon wafer.

Many samples can be made at the same time on the same wafer, generating a quantity of adhesion data in a timely fashion.

To study fatigue failure — a common failure mode wherein delamination occurs over time with repeated heating and cooling cycles, Sitaraman and Ostrowicki plan to cycle the electromagnet’s voltage on and off. “A lot of times, layers do not delaminate in one shot,” Sitaraman said. “We can test the interface over hundreds or thousands of cycles to see how long it will take to delaminate and for that delamination damage to grow.”

The test station fits into an environmental chamber, allowing the researchers to evaluate harsh-environment electronics under the effects of high temperature and/or high humidity. “We can see how the adhesion strength changes or the interfacial fracture toughness varies with temperature and humidity for a wide range of materials,” Sitaraman explained.

Sitaraman and Ostrowicki have studied thin film layers about one micron in thickness, but say their technique will work on layers that are of sub-micron thickness. Because their test layers are made using standard microelectronic fabrication techniques in Georgia Tech’s clean rooms, Sitaraman believes they accurately represent the conditions of real devices. These are representative processes and representative materials, mimicking the processing conditions and techniques used in actual microelectronics fabrication.

“As we continue to scale down the transistor sizes in microelectronics, the layers will get thinner and thinner,” he said. “Getting to the nitty-gritty detail of adhesion strength for these layers is where the challenge is. This technique opens up new avenues.”

The research has been supported by the National Science Foundation, and was reported in the March 30, 2012 issue of the journal Thin Solid Films.

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