April 9, 2012 — Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment (WFE) spending, with a look at the top players and underlying trends by process step. Here, Barclays’ CJ Muse explains changes at the etch step.
Wafer etch intensity (% of total WFE spending) declined to ~13.8% from 2010 to 2011. However, long-term, etch intensity will improve, at least until the onset of extreme ultra violet lithography (EUVL).
As advanced DRAM and Logic utilize more litho etch litho etch (LELE) double patterning and as NAND Flash chips utilize more self aligned double patterning (SADP) lithography, the number of etch steps performed per semiconductor wafer double. Why didn’t this trend occur in 2011? Muse blames it on the process control focus of 2011, where yield was the central issue.
In 2012, 3x DRAM, 2x NAND Flash, and advanced logic will ramp in volumes, utilizing advanced high-k metal gate (HKMG) architectures. Etch should see benefits as capacity additions are incorporated.
Silicon etch grew in 2011, now making up ~47% of etch, while dielectric etch saw steady declines, dropping to ~49% of the market in 2011. Silicon etch will continue to grow market share within etch.
For information on the top players (Lam Research’s market share and possible inroads at Intel), read Wafer fab equipment leaders in 2011 and expectations for 2012
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