ITF: The technology knobs for system scaling

In an exclusive series of blogs, imec’s science writers report from the International Technology Forum (ITF) in Brussels. This year, ITF’s theme was “It’s a changing world. Let’s make a sustainable change together”.

Tomorrow’s data centers and smart mobile devices will require extreme computation and storage capabilities, orders of magnitude above what today’s processors and memories can deliver. This drives the need to keep on scaling technologies. In her ITF presentation, An Steegen, Senior Vice President Process Technology at imec, discusses the three technology knobs that are key for a further system scaling.

First, in pursuit of Gordon Moore’s law, there is area scaling. Lines and spaces within the transistor will become smaller and smaller, and the specs for overlay – how the lines and spaces are aligned to each other – get ever more severe. Where in 1985, technologists could still live with 300nm overlay for a 1000nm technology on a 100mm Si wafer, the overlay spec has gone down to 5nm for a 20nm CMOS node in 2013. Advanced lithography is the key knob to get there, and for future nodes, EUV shows great capabilities. With one single exposure, it promises to go down to 16nm lines and spaces, and reach less than 2nm overlay.

A second technology knob is power/performance trade-off. Reaching increasing computation power requires a look into new materials and device architectures. For the 32/28nm technology node, the semiconductor industry did so by introducing high-k/metal gates. Moving on to the 22/14nm, fully depleted devices such as the FinFET are being implemented, allowing to improve the transistor’s sub-threshold slope and electrostatic behavior. Moving further, higher mobility channels will be inserted as a replacement for the Si channel. Beyond 10nm, technologists will have to move away from the solid-state based transistors, and go into other mechanisms like quantum-mechanical tunneling. And very far out, more novel materials such as graphene will probably take over. But also the back-end and interconnections will require material innovations, such as moving away from Cu metallization for reliability reasons, and moving into ultralow-k materials as a dielectric. One new area that comes along is variability and how to deal with it when moving forward into these very small devices.

Last but not least, there is cost as a third technology knob. How to keep the cost factor under control when the roadmap gets ever more complicated? Well, inserting EUV e.g. at the 14nm node will certainly help, as cost analysis has shown. Of course, there is the question of 450mm: is economy of scale also helping us out to scale our future technology nodes?

The challenges for scaling are huge, but imec is confident that, together with its partners, they will find the right solutions. They did so in the past, when scaling was considered to already have reached its limits. Today, it will be just a little harder than it used to be.

Mieke Van Bavel, science editor, imec, Belgium


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