Bridging the fabless-foundry gap: Highlighted ConFab presentation

May 18, 2012 — At The ConFab, an invitation-only semiconductor industry event June 3-6 in Las Vegas, TSMC’s BJ Woo, senior director, Graphic/PLD/CPU Business Development Division, will present “Bridging the Fabless-Foundry Gap.”

Woo will speak in Session #3: The Foundry-Fabless Supply Chain, alongside Nick Yu, VP of technology development, Qualcomm; Mike Noonen, senior VP, worldwide sales & marketing, GLOBALFOUNDRIES; and Xin Wu, senior director, silicon technology, Xilinx Inc.

“Bridging the gap between fabless design houses and foundry is the essential factor of the winning strategy,” Woo says. Fabless design houses and foundries need to collaborate closely to deliver successful semiconductor products and to prosper together. She will specify the requirements and challenges for chip designers as the complexity of technology grows in advanced nodes. She will also present solutions to address those challenges, showing how fables companies and foundry can collaborate and succeed.

For fabless design houses, major concerns include competitive technology selection with best performance/watt/cost, first silicon success to enable fast time to market and stable/reliable supply support with decent yield and ample capacity to secure market segment share.

Foundries will provide multiple process options with customization to address the unique requirements for different product applications. Meanwhile, accurate SPICE model, design for manufacturing (DFM), and intellectual property (IP) validation will help improve first silicon success rate and time to market. 

Stable/ reliable supply is one of the keys for fabless companies to gain and secure market segment share. As such, foundry businesses need to provide a more sophisticated manufacturing infrastructure to go after the best manufacturing excellence. Such infrastructure includes fully automated manufacturing systems, Giga-fabs for large scales of economy, speedy productization from tapeout to volume production, steep yield learning curve, nano-scale precision control for yields and technology scaling, product-grade enhancement, and integrated service (mask, wafer, and backend) for coherent quality and delivery.

Fabless and foundry companies need to collaborate closely in design, technology, and manufacturing areas to deliver a successful product with best performance/watt/cost and, in turn, to compete and to win in the marketplace. In addition, sufficient and reliable capacity support with manufacturing excellence will grow customers, growing business.

BJ joined TSMC as Senior Director of Technology Roadmap Division in April 2009.  She is currently in charge of the High Performance Technology definition for Graphics, PLD, CPU and Game Console Business Development Division. Prior to joining TSMC, BJ has spent most of her career in Intel Corp., 24+ years. Because of her excellent work and leadership, she was nominated by Intel and was honored as 2006 inductee Hall of Fame for WITI (women-in-technology-international).

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