Conference Report: IITC, Day 2

Day 2 of the 15th IITC (International Interconnect Technology Conference) opened Tuesday, June 5 at the Doubletree Hotel in San Jose, CA under mostly sunny skies and a pleasant breeze.

Prof. Bill Dally of Stanford U and Chief Scientist at Nvidia delivered a keynote address on the architect’s view of interconnect: it’s about the power. The end of historic device scaling can be identified as 2005 based on a number of performance and design parameters. Scaling today is tracking at a 3x power density increase per node, so that devices today are power limited rather than area limited. Data movement, i.e. reading and writing information, requires significantly more power than operating on it in the CPU. His recommended strategy toward a solution is to view this as an interconnect problem rather than as a memory problem. Architecture can reduce the need for data movement. Profiling the applications to be run on a particular device can suggest, for example, a cache size and implementation choice that will reduce energy consumption up to 30% without changing a single line of code. This takes place within the on-chip network. Connecting functional modules in a mesh network (he showed one called the flattened butterfly topology; no insects were harmed during the presentation) rather than through a linear bus is another source of energy efficiency gain. “A joule is a terrible thing to waste; driving a bit with a high voltage swing is as bad as driving a Hummer.” Low voltage swing interconnect drivers is one focus area of his research. Bill envisions that energy efficiency improvements in interconnects will come 4x from process/materials, 5x from circuit design and 5x from architecture.

Keren Bergmen of Columbia U gave an invited talk on the use of nanophotonic interconnect networks for optimizing performance & energy in computing. Processor pin count demands for high performance operations exceed the ITRS projections well before 2016. Photonic interconnects hold a bandwidth promise of 2 Tbps/20µm pitch at the chip’s edge. Creating an optical network based on electronic design principles fails to leverage the unique characteristics that optics can bring to the table. New design tools are being developed to correct this oversight. 3D optical interconnect networks are being evaluated as an evolution of single plane optical systems. Such deposition-based silicon-photonic systems allow the optical network to be integrated into the on-chip interconnect stack while releasing the optical design from the groundrule restrictions of the electronic elements. Simply substituting optical channels for copper interconnects will not produce the gains needed.

Michele Stucchi of IMEC described the impact of 193nm and EUV lithography options on local interconnect performance. The alternating line dimensions resulting from double patterning schemes introduce a performance variability that is not present in EUV single exposure. R, C, RC and coupling parameters have been extracted from models of LELE, SDDP and EUV processes. Overlay variations impose a significant penalty on the LELE sequence. SDDP and EUV are still considered to be viable options for large scale manufacturing yield and reliability.



Akihiro Kojima of Toshiba switched technology domains with a discussion of a WLP technology for low-cost solid state LED lighting. The LED is formed in a GaN epi layer grown on sapphire with a copper M1 interconnect and pillar, and encapsulated. The devices are inverted, the sapphire carrier is removed by excimer laser liftoff, and the phosphor is applied to the exposed GaN devices. Light output is 20% higher than conventional constructs. Thermal resistance is as low as 24.2°K/W. The package can accommodate an input power of 2.1W, for a power density equivalent of 1157W/cm2.

Tsuyoshi Kanki of Fujitsu Labs described a highly reliable chip-to-chip interconnect technology using 1µm L/S. The secret sauce is a copper plating process that reduces the halogen ion content of the dielectric resin, and encapsulating the Cu features in CoWP or NiP. The resulting combinations show leakage currents of <1×10-9amps over 160 hours electrical stress, with the CoWP holding steady at 1×10-10amps.

KN Chen of National Chiao Tung U (Taiwan) delivered an invited talk on the electrical performance and quality of integrated bonded structures for 3D and TSV interconnects. Design options included oxide recess, lock & key, and lock & key with adhesive. Material bonding systems were Cu-Cu, Cu-Sn micro bumps and Cu alloy. The data indicates that reliable structures can be achieved with the appropriate system-specific trade-offs. Co-sputtered Cu/Ti with a self-formed Ti adhesion layer was a favored construct.

Dan Edelstein of IBM Watson Research gave an invited talk on engineering the extendibility of Cu/low-κ interconnect technology. The minimum Cu wire width for the 10nm node is 20× smaller than when Cu interconnects were first introduced. Modification of the dielectric precursors to incorporate a porogen skeleton has moved κ from 2.5 to 2.35 without a loss in modulus. Copper reflow <250°C is another process tweak proving useful for defect-free metallization. Co liners are subject to galvanic corrosion that exacerbates electromigration problems, and so remains to be solved. CuMn is thought to be extendible to the 14nm node. Work on modified ULK materials with pore sizes in the tenths of nanometers shows a strong correlation between pore size and distribution with TDDB.

P. Casey of Dublin City U (Ireland) conducted studies on Mn silicate layer formation on SiO2 using synchrotron photoemission spectroscopy, XPS and TEM. They found no evidence for the formation of Mn oxides; all of the Mn formed the silicate in a self-limited reaction. A pure metal 1nm Mn film cannot be fully converted to the silicate with 500°C anneal, whereas a 1nm partially oxidized Mn film can be. Fully oxidized Mn can also be converted to MnSiO3 without the presence of metallic Mn.

Sang Hoon Ahn of Samsung R&D described the recovery of acceptable TDDB performance following its moisture-induced degradation in a Cu/ULK (κ 2.5) system. The moisture showed up as an increase in leakage current and a decrease in Vrdb (voltage ramp dielectric breakdown). A low damaging UV treatment combined with a mild remote hydrogen plasma treatment restored Vrdb and TDDB to their pre-damage levels.

Prof. Akira Uedono of U Tsukuba (Japan) spoke on the agglomeration and dissociation of vacancies in electroless deposited Cu films studied by positron annihilation. The technique was shown to be effective for characterizing vacancies in the Cu films, which in turn can be used to guide additives and formulations for electroless deposition. Appropriate residual impurities can lead to the formation of stable vacancy-impurity complexes that can suppress vacancy migration and improve resistance to electromigration. Analogous studies on electroplated Cu have shown comparable vacancy characteristics, but also suggest that there has been little progress in electroplated copper formulations with respect to vacancy formation over the past decade.

Axel Preusse of GlobalFoundries addressed metallization and reliability challenges in current and near-future nodes. The familiar litany of challenges overwhelmed the list of prospective solutions, which itself is becoming familiar. The good news is that there are still plenty of knobs to turn, at least down to 20nm.

Koichi Motoyama of Renesas presented a novel Cu reflow seed process for dual damascene interconnects at 64nm and beyond. Via chain yield improved by ~60% for dense via chains and ~70% for isolated chains. A low bias Cu underlayer deposition is required prior to the high bias Cu/Ar+ resputtering and reflow in order to prevent barrier damage at the top corners of the via. Reflow was conducted ~250°C.


Hideharu Shimizu of Taiyo Nippon Sanso conducted a comparative study on ALD/CVD Co(W) films as a single barrier/liner layer for 22nm interconnects and beyond. Carbonyl and metallocene precursors were compared, with nominal targets of 10at% W and 20at% W in Co. Addition of W improved the barrier properties of both CVD and ALD Co. However, addition of W increased the activation energy for Cu diffusion into ALD-Co(W) whereas it did not change in CVD-Co(W) due to better W filling of the ALD grain boundaries. ALD-Co(W) also has lower resistivity because the precursor reaction path can minimize the inclusion of oxygen in the film. Adhesion of Cu to ALD-Co(W) was superior to that of PVD-Ta, consistent with wetting angles observed on the two surfaces.


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