If you want to quickly find and fix the source of a process excursion, you have to be able to capture the right defects, and review and classify them efficiently. Electron-beam review is always the rate-limiting step in this process; thus it’s worth investing effort in improving the odds of identifying defects that are going to lead to discovery of the source of the excursion. Even at the blinding speed of up to12,000 defects per hour (the state of the art for an e-beam review tool), most fabs can’t justify the time to review every defect on every wafer. How do you make sure you’re reviewing the yield killing defects and not wasting time reviewing nuisance events?
On critical layers, optical wafer inspection has to be run very “hot,” that is, with very high sensitivity settings, in order to capture the smallest, lowest-contrast defects that may affect yield. The problem is that hot inspections frequently capture not only defects of interest (DOI), but also nuisance events, such as line-edge roughness or defects on dummy pattern. Unfortunately, nuisance events tend to strongly dominate the defect count in a hot inspection. When it comes time to review the defects to determine their source, choosing a random, unbiased sample may lead to reviewing a very small number of DOI—perhaps too small to represent the DOI population accurately. You might not even be lucky enough to sample all DOI defect types, if nuisance defects represent a large fraction of the defects captured. The result is a misleading defect pareto—which can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market.
There are two main approaches to skew the defect pareto away from nuisance events and toward DOI: (1) reduce the percent nuisance capture on the inspection system and (2) identify nuisance events after inspection and remove them from the review sample. A third approach would be to identify nuisance defects during e-beam review, but that strategy would be the least efficient. Nuisance capture on the inspection system can be reduced by selecting an appropriate combination of inspection wavelengths, apertures and polarizations that preferentially captures DOI over nuisance. Having an inspection system that offers the flexibility to manipulate defect type capture can be very effective at reducing nuisance capture during inspection. This sort of approach has been used for many device generations and over many generations of inspection systems for nuisance reduction.
What’s new is the ability to use design information to either skip “nuisance areas” of the die during inspection—or, after inspection, to remove defects residing in nuisance areas from the review sample. The former strategy is called micro-care area inspection; the latter is called design-aware nuisance filtering.
One of our technology-leading customers recently used micro-care area inspection to focus a high sensitivity inspection on patterns comprised of dense, thin lines. An automatic “care area” generator was used to search through the design file of the die, to draw hundreds of thousands of small care areas wherever dense, thin lines occurred (Figure 1). Only these care areas would be inspected. Together the care areas represented less than 5% of the die area normally inspected—but defects occurring in these areas had a high probability of being yield killers. Severely restricting the inspected areas dramatically increased capture of the yield-killing bridge defects and reduced the nuisance defect population to nominal levels.
Design-aware nuisance filtering was used to help two prominent foundries reduce nuisance defects on a silicon-germanium (SiGe) layer. SiGe is used in some high K metal gate processes to improve device performance. The problematic nuisance defect on the SiGe layer represented a small change in shape to the edge of the polygon—a variation that had no apparent effect on the device. After the defect team optimized the wavelength/aperture/polarization combination for best capture of DOI, traditional nuisance filtering, based on the attributes of the defect signal during inspection, was able to reduce the nuisance defect count by an order of magnitude. However, nuisance events still dominated the captured defect population, at a rate of 90%. At this point, design-aware nuisance filtering was used to associate the locations of the nuisance defects to a small number of pattern types. When all inspection events associated with these pattern types were eliminated, the DOI contribution to the defect pareto advanced from 10% to 85%. Two SiGe nuisance areas are indicated in Figure 2 with solid yellow lines.
Strategically manipulating the defect sample reviewed by the e-beam review system so that it contains a high percentage of DOI has become necessary to creating a defect pareto that quickly and clearly directs defect engineers to the source of the excursion. Techniques like micro-care area inspection and design-aware nuisance filtering can be valuable tools for skewing the defect pareto toward yield-killing defects. For further information about creating an actionable defect pareto, please see last month’s Process Watch article, “The Dangerous Disappearing Defect.”
Rebecca Howland, Ph.D., is a senior director in the corporate group and Ellis Chang, Ph.D., is Nuisance Czar in the wafer inspection division at KLA-Tencor.
Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.
Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”