Multitest releases 3D packaging test combination for sensitive bare die

July 9, 2012 — Semiconductor test equipment supplier Multitest installed the first Multitest Plug & Yield integrated hardware set up for testing 3D semiconductor packages at a customer. The Plug & Yield design enables highly parallel electrical in-process test of stacked dies during the assembly process of 3D packages.

The hardware set up comprises a Multitest InStrip3D, a test interface board, and a contacting solution based on vertical spring technology. The system will be used to electrically test partial stacks during assembly of a mobile SoC.

The integrated test solution uses a Multitest load board, which has fine-pitch, high layer count PCBs to support this 0.4mm pitch array application in a high-pin-count multi-site configuration. In close cooperation with the customer, the mechanics of the test were redesigned to accommodate the increased forces from the highly dense pogo array of approximately 6000 pins.

The InStrip3D, part of Multitest

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