STATS ChipPAC expands TSV work into mid-end-of-line

August 29, 2012 – STATS ChipPAC, Fremont, CA, says it has expanded its through-silicon via (TSV) capabilities by qualifying a 300mm mid-end manufacturing operation and transition to low-volume manufacturing.

STATS ChipPAC was one of the first outsourced semiconductor assembly and test (OSAT) providers to invest in through-silicon via (TSV) technology for back-end-of-line (BEOL) semiconductor manufacturing, specifically 2.5D (silicon interposers) and 3D TSV on 200mm wafers, with chip/chip and chip/wafer assembly using stealth dicing and fine-pitch microbump bonding down to 40μm. A year ago the company began expanding into TSVs for 300mm mid-end-of-line (MEOL) processing capabilities, steps that occur between wafer fabrication and back-end assembly. These include microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.

"During the implementation phase of our mid-end TSV operation, we investigated multiple process options and identified key cost variables that would affect the commercialization of this technology," said Dr. Han Byung Joon, STATS ChipPAC’s EVP and CTO. "We now have mid-end manufacturing capacity in place in Singapore and are actively engaged with multiple strategic customers on the production qualification of 2.5D and 3D packaging designs."

The company says it is "firmly engaged with multiple strategic customers" in TSV development programs. Current 3D TSV development and customer qualification activities include devices at the 28nm silicon node, application processors and graphic processors utilizing TSV to match the needs of higher-bandwidth applications for the mobile market.

(Image via Stats ChipPAC)


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