Advancing CNTs for next-gen chips

November 8, 2012 – Researchers from IBM and Georgia Tech have disclosed significant progress in manipulating carbon nanotubes in transistors and interconnects, in ways compatible with traditional fabrication techniques, advancing toward using the materials for next-generation devices.

Connecting nanotubes to semiconducting substrate

Researchers from Georgia Tech say they have achieved a first: connecting multiple shells of a multiwalled carbon nanotube (MWCNT) to a semiconducting substrate without the high interface resistance produced by traditional fabrication technique — showing a way, they say, to facilitate integration of CNTs as interconnects in next-generation circuitry using both silicon and carbon components.

The work, reported online by the journal IEEE Transactions on Nanotechnology, uses electron beam-induced deposition (EBID), develops graphitic nanojoints on both ends of the MWCNTs, yielding a 10-fold decrease in resistivity in the connection to metal junctions. The technique "is amenable to integration with conventional integrated circuit microfabrication processes," explained prof. Andrei Fedorov. "Connecting to multiple shells allows us to dramatically reduce the resistance and move to the next level of device performance."

The low-temperature EBID process takes place in a scanning electron microscope (SEM) modified for material deposition — the vacuum chamber is altered to introduce materials precursors and the electron gun generates low-energy secondary electrons when the high-energy primary electrons impinge on the substrate at specific locations. When the secondary electrons interact with hydrocarbon precursor molecules, carbon is deposited with a strong, chemically-bonded connection to the ends of the carbon nanotubes, unlike the weakly-coupled physical interface made in traditional techniques based on metal evaporation, the researchers say. Prior to deposition, the ends of the nanotubes are etched opened so the deposited carbon grows into the open end of the nanotube to electronically connect multiple shells. Thermal annealing of the carbon after deposition converts it to a crystalline graphitic form that significantly improves electrical conductivity.

"Atom-by-atom, we can build the connection where the electron beam strikes right near the open end of the carbon nanotubes," Fedorov explained. "The highest rate of deposition occurs where the concentration of precursor is high and there are a lot of secondary electrons. This provides a nanoscale sculpturing tool with three-dimensional control for connecting the open ends of carbon nanotubes on any desired substrate."

The technique produces record low resistivity at the connection between the carbon nanotube and the metal pad — the researchers have measured resistance as low as ~100 Ohms, a factor of ten lower than the best that had been measured with other connection techniques.

This is still very early work, though. The researchers don’t know exactly how many of the CNT shells are connected (they think at least 10 out of 30 "are contributing to electrical conduction). And converting the birds’ nest of tangled CNTs of different lengths, properties and defectivity into a pattern for reliable interconnects is a challenge. The team says it has developed a method to align the MWCNTs across electrical contacts using focused electrical fields in combination with a substrate template created through electron beam lithography, which has "significantly improved yield of properly aligned carbon nanotubes." But much work needs to be done to improve CNT alignment, and perfect EBID systems to deposit connectors on multiple devices simultaneously (parallel electron beam systems might help here).

"A major amount of work remains to be done in this area, but we believe this is possible if industry becomes interested," Federov said. "This is really a critical step for making many different kinds of devices using carbon nanotubes or graphene."


Two SEM images showing a carbon nanotube interconnect done with the EBID process.
(Source: Georgia Tech)

Precisely placed, high-density CNT transistors

IBM, meanwhile, says it’s made a leap toward viability of carbon nanotube (CNT) transistors, by precisely placing and testing thousands of CNTs in a single chip using standard semiconductor processes.

The ability to isolate semiconducting nanotubes and precisely place them in high density on predetermined positions on a wafer is critical to assessing their suitability. So far scientists have only placed a few hundred CNT devices at a time, not enough to assess key issues for commercial application — and far below the millions or even billions of transistors eventually needed for future chips.

Earlier this year IBM showed a sub-10 nm CNT transistor showing 5-10× better performance than silicon circuits. The group’s newest work, detailed in the journal Nature Nanotechnology, describes an ion-exchange chemistry that allows precise, controlled placement of aligned carbon nanotubes on a substrate, with a high density (109/cm2) that’s 2 orders-of-magnitude greater than previous experiments.

The process involves mixing the CNTs with a surfactant to make them soluble in water. A substrate with trenches of chemically-modified HfO2 (and SiO2 everywhere else) is immersed in the solution, and the CNTs attach via chemical bond to the HfO2 regions; the rest of the surface remains clean. The new placement technique can be readily implemented since it involves common chemicals and existing semiconductor fabrication, IBM says, and compatibility with standard commercial processes also means rapid testing with high-volume characterization tools.

Carbon nanotubes "have largely been laboratory curiosities as far as microelectronic applications are concerned," acknowledged Supratik Guha, director of physical sciences at IBM Research. This new IBM work makes "significant strides" in solving two key challenges of ultrahigh-purity CNTs and their deliberate nanoscale placement, and thus represents "the first steps towards a technology by fabricating carbon nanotube transistors within a conventional wafer fabrication infrastructure."

SEM image of carbon nanotubes deposited on a trench coated in hafnium oxide (HfO2) showing extremely high density and excellent selectivity. Scale bar: 2μm. (Credit: IBM)


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