TSMC’s Integrated 16nm FinFET Technology Platform: Gain in transistor performance traditionally have come from scaling the devices smaller, but with today’s nanoscale-sized features that has become difficult. New transistor architectures such as multiple-gate devices are an alternative. When more than one gate controls the flow of electrons and holes though a transistor’s channel, better on/off control can be achieved. This allows for higher drive currents or lower supply voltages than otherwise possible, and makes the devices potentially suitable for a range of applications. (Multiple-gate devices are often called FinFETs because they feature a long, thin channel that resembles a shark’s fin.) At the IEDM, TSMC researchers will describe a 16nm FinFET process that by many measures is one of the world’s most advanced semiconductor technologies. In size, it is the first integrated technology platform to be announced below the 20nm node, with key features including a 48nm fin pitch and the smallest SRAM ever incorporated into an integrated process—a 128Mb SRAM measuring 0.07 µm2 per bit. In performance, it demonstrated either a 35% speed gain or a 55% power reduction over TSMC’s existing 28nm high-k/metal gate planar process, itself a highly advanced technology, and had twice the transistor density. Short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 uA/um at 0.75V (NMOS and PMOS, respectively) and off-current of 30 pA/um. It incorporates seven levels of high-density copper/low k interconnect and high-density planar MIM devices for noise control.
The left image shows that the 16nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process. The right set of images show a cross-section of the device’s 7-level metal copper/low-k architecture, with low resistance.
(Paper #9.1, “A 16nm CMOS FinFET Technology for Mobile SoC and Computing Applications,” S-Y. Wu et al, Taiwan Semiconductor Manufacturing Co.)