#4: Monolithic 3D Chip

Slide 4-1 Slide 4-2

Monolithic 3D Chip: An alternative to scaling is to expand vertically. Although 3D circuits often are made by stacking separate chips and connecting them with through-silicon vias (TSVs), some TSVs also have major disadvantages, including relatively large dimensions, parasitic capacitances and thermal mismatch issues. Researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories. They built it from ultrathin-body MOSFETs isolated by 300nm-thick interlayer dielectric layers. To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.

The image above left illustrates the process flow, while the image on the right is a TEM electron microscope view of the 3D chip.

(Paper #9.3, “Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM,” C–H. Shen et al, National Nano Device Laboratories)

<< Previous                        Next>>

Jump to Page [1]   [2]   [3]   [4]   [5]    [6]   [7]   [8]   [9]   [10]   [11]


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.