#8: 300mm wafer-scale Ge FinFET

Slide 8

300mm wafer-scale Ge FinFET: One of the main challenges to the use of Ge in advanced devices is the need for a cost-effective and manufacturable method to integrate highly crystalline Ge on a silicon wafer. At last year’s IEDM, TSMC described the successful integration of p-channel Ge FinFETs on 300mm silicon wafers using an aspect ratio defect-trapping method. This year, they improved the performance of p-channel Ge FinFETs by implementing: 1) an optimized 8-angstrom capacitance-equivalent thickness gate stack fabricated with a replacement-gate process; 2) a scaled-down fin width; and 3) the <110> crystal direction in the channel. Compared to any other reported non-silicon pFET, the 20nm-channel-length FinFETs demonstrated 2.5 times better subthreshhold slope performance, twice the on/off current and record electrical conductance of 2.7mS/µm.

The figure above shows that the transconductance (transport properties) of the p-channel Ge FinFETs is better than any previously reported data at a given subthreshold slope (short channel effects).  The right side of the figure then adjusts the transconductance for the difference in gate oxide thickness, and makes the point that it still shows the advantage over the previous work.

(Paper #20.1, “Scaled P-Channel Ge FinFET With Optimized Gate Stack and Record Performance Integrated on 300mm Si Wafers,” B. Duriez et al, TSMC)

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