IEDM 2012 slideshow 08

Sub-40nm 3D NAND

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at IEDM. They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction, and improves manufacturability. The new architecture also enables the use of a novel "staircase" bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75nm, 64 cells per string, and a core array efficiency of 63%. The technology not only is lower-cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes, according to the researchers. At that size this device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density. (#2.3: "Highly Scalable 8-Layer Vertical-Gate 3D NAND With Split-Page Bit Line Layout and Efficient Binary-Sum MiLC (Minimal Incremental Layer Cost) Staircase Contacts")


An overview of the proposed architectural layout — twisted even/odd bitline (split-page) VG architecture — that is said to be an improvement on previously proposed 3D vertical gate NAND architecture. The even/odd island gate SSL devices can be laid out in double pitch, providing much larger process window for BL pitch scaling.

<<<     PREV      1  2  3  4  5  6  7  8  9  10  11  12  13  14     NEXT     >>>>


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.