3D integration with TSVs, chip-on-wafer
In this paper, TSMC describe an advanced 3D integration process featuring through-silicon via (TSV) and chip-on-wafer (CoW) technologies, analyzing the impact of wafer thinning, stacking, and TSV proximity effects to poly and high-k/metal gate (HKMG) CMOS devices. Using this 3D process, poly and HKMG CMOS wafers have been successfully thinned and stacked, showing little to no degradation in the process. The effect of TSV-induced mechanical stress on ΔIdsat for HKMG was found to be smaller as normalized to poly gate devices for the same channel length (ΔIdsat ratio of HKMG to poly is ~0.3 and ~0.5 for PMOS and NMOS, respectively). They also will show that ΔIdsat for HKMG device is proportional to TSV surface area, independent of TSV orientation, device polarity, and distance of device from TSV. (#33.4: "Thinning, Stacking, and TSV Proximity Effects for Poly and high-k/Metal Gate CMOS Devices in an Advanced 3D Integration Process")
SEM image of a nanowire resonator (2.3μm × 65nm × 45nm). Electromechanical coupling is achieved through ~60nm flexible airgap capacitors. The nanowire resonates in-plane.