Cadence unveils Virtuoso Advanced Node for 20nm design

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the availability of Virtuoso® Advanced Node, a new set of custom/analog capabilities designed for the advanced technology nodes of 20nm and below.Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter® RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of mixed-signal chips that power today’s consumer electronics devices.

The new and advanced Virtuoso technologies address layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate with the Cadence Integrated Physical Verification System (IPVS) to conduct on-the-fly checks that reduce layout iterations.

LDE analysis using incremental layout — Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end.  It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.  LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics — are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time.  By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.

Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.

“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28nm on the same circuit,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.”


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